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1.发明授权公开(公告)号：US09166590B1
公开(公告)日：2015-10-20
申请号：US14162037
申请日：2014-01-23
Applicant: Altera Corporation
Inventor： Chee Wai Yap , Muhamad Aidil Jazmi
IPC: H03K19/003 , H03K19/0175
CPC classification number: H03K19/017581
Abstract: An integrated circuit may include memory interface circuitry that interfaces with memory. The integrated circuit may include calibration circuitry and storage circuitry. The calibration circuitry may have a first configuration in which the calibration circuitry is formed from a first set of programmable logic regions that configure the calibration circuitry to generate and store calibration data at the storage circuitry. The calibration data may include strobe signal phase settings and read enable control signal timing settings. The calibration circuitry may have a second configuration in which the calibration circuitry is formed from a second set of programmable logic regions that configure the calibration circuitry to load the calibration data from the storage circuitry and to interface with the memory based on the calibration data. The calibration circuitry may occupy fewer programmable logic regions on the integrated circuit in the second configuration than in the first configuration.
Abstract translation: 集成电路可以包括与存储器接口的存储器接口电路。 集成电路可以包括校准电路和存储电路。 校准电路可以具有第一配置，其中校准电路由配置校准电路的第一组可编程逻辑区形成，以在存储电路上生成和存储校准数据。 校准数据可以包括选通信号相位设置和读使能控制信号定时设置。 校准电路可以具有第二配置，其中校准电路由第二组可编程逻辑区域形成，第二组可编程逻辑区域配置校准电路以从存储电路加载校准数据，并且基于校准数据与存储器接口。 在第二配置中，校准电路可能占用集成电路上的可编程逻辑区域少于在第一配置中。
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公开(公告)号：US09300463B2
公开(公告)日：2016-03-29
申请号：US14271348
申请日：2014-05-06
Applicant: Altera Corporation
Inventor： Boon Hong Oh , Chee Wai Yap
CPC classification number: H04L7/0332 , G09G5/006 , G09G2370/10 , H03M9/00 , H04L7/0087 , H04N7/015
Abstract: Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include a receiver circuit and one of the provided techniques includes receiving a data stream at the receiver circuit. The receiver circuit may include a detector circuit that is used to determine the data rate of the received data stream. A controller block in the receiver circuit may accordingly configure a deserializer circuit in the receiver circuit based on the data rate of the received data stream. The circuitry may further include a transmitter circuit for transmitting data streams. The transmitter circuit may be configured during runtime based on the data rate of a data stream that is being transmitted. In some instances, irrespective of the data rate of the data stream being transmitted, a constant reference clock may be used in the transmitter circuit.
Abstract translation: 提供了在集成电路中操作电路的技术。 电路可以包括接收器电路，并且所提供的技术之一包括在接收器电路处接收数据流。 接收器电路可以包括用于确定接收的数据流的数据速率的检测器电路。 因此接收机电路中的控制器块可以相应地基于所接收的数据流的数据速率来配置接收机电路中的解串行电路。 电路还可以包括用于传输数据流的发射机电路。 发射机电路可以在运行期间根据正被发送的数据流的数据速率进行配置。 在一些情况下，不管发送的数据流的数据速率如何，在发射机电路中可以使用恒定的参考时钟。
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公开(公告)号：US09197210B1
公开(公告)日：2015-11-24
申请号：US14223949
申请日：2014-03-24
Applicant: Altera Corporation
Inventor： Chee Wai Yap
IPC: H03K19/177 , H03K19/173 , H03K19/00
CPC classification number: H03K19/0008 , H03K19/17772 , H03K19/17784
Abstract: Apparatuses for reducing power consumption in a programmable logic device (PLD) with a self power down mechanism are disclosed. Methods and a machine readable medium for restoring a prior known state are provided. The prior known state is stored in a memory module before the PLD is powered down and the same state is restored from the memory module when the PLD is powered up. The memory module may be an internal or an external non-volatile or volatile memory source. One sector of the memory may be used to store the previous known state. The memory sector can be partitioned into different sections. One section may be used as a header section associated with a data storage section. Partitioning the memory sector into different sections and utilizing multiple addresses from each section ensure less read and write cycles during the powering down and the powering up of the PLD.
Abstract translation: 公开了一种在具有自省电机构的可编程逻辑器件（PLD）中降低功耗的装置。 提供了用于恢复先前已知状态的方法和机器可读介质。 在PLD断电之前，先前已知的状态被存储在存储器模块中，并且当PLD通电时，从存储器模块恢复相同的状态。 存储器模块可以是内部或外部非易失性或易失性存储器源。 存储器的一个扇区可以用于存储先前已知的状态。 内存扇区可以划分成不同的部分。 一个部分可以用作与数据存储部分相关联的标题部分。 将存储器扇区分成不同的部分，并利用每个部分的多个地址，确保在断电和PLD加电期间读取和写入周期更少。
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Patent Agency Ranking
公开(公告)号：US20150288511A1
公开(公告)日：2015-10-08
申请号：US14271348
申请日：2014-05-06
Applicant: Altera Corporation
Inventor： Boon Hong Oh , Chee Wai Yap
CPC classification number: H04L7/0332 , G09G5/006 , G09G2370/10 , H03M9/00 , H04L7/0087 , H04N7/015
Abstract: Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include a receiver circuit and one of the provided techniques includes receiving a data stream at the receiver circuit. The receiver circuit may include a detector circuit that is used to determine the data rate of the received data stream. A controller block in the receiver circuit may accordingly configure a deserializer circuit in the receiver circuit based on the data rate of the received data stream. The circuitry may further include a transmitter circuit for transmitting data streams. The transmitter circuit may be configured during runtime based on the data rate of a data stream that is being transmitted. In some instances, irrespective of the data rate of the data stream being transmitted, a constant reference clock may be used in the transmitter circuit.
Abstract translation: 提供了在集成电路中操作电路的技术。 电路可以包括接收器电路，并且所提供的技术之一包括在接收器电路处接收数据流。 接收器电路可以包括用于确定接收的数据流的数据速率的检测器电路。 因此接收机电路中的控制器块可以相应地基于所接收的数据流的数据速率来配置接收机电路中的解串行电路。 电路还可以包括用于传输数据流的发射机电路。 发射机电路可以在运行期间根据正被发送的数据流的数据速率进行配置。 在一些情况下，不管发送的数据流的数据速率如何，在发射机电路中可以使用恒定的参考时钟。
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公开(公告)号：US10439795B2
公开(公告)日：2019-10-08
申请号：US15826472
申请日：2017-11-29
Applicant: Altera Corporation
Inventor： Boon Hong Oh , Chee Wai Yap
Abstract: Circuitry and methods of operation thereof for video communication are described herein. The circuitry described herein may be programmable circuitry. The circuitry may include a receiver circuit and/or a transmitter circuit and one of the provided techniques includes receiving and/or transmitting video data. The receiver circuit may include a detector circuit that is used to determine the data rate of the received video data stream. The circuitry may further include a transmitter circuit for transmitting data streams. The transmitter circuit may be configured during runtime based on the data rate of a data stream that is being transmitted. The data rate of the video data stream may be associated with a video standard. In some instances, irrespective of the data rate of the data stream being transmitted, a constant reference clock may be used in the transmitter circuit. The circuitry discussed herein can support multiple protocol data paths.
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公开(公告)号：US20180083765A1
公开(公告)日：2018-03-22
申请号：US15826472
申请日：2017-11-29
Applicant: Altera Corporation
Inventor： Boon Hong Oh , Chee Wai Yap
CPC classification number: H04L7/0332 , G09G5/006 , G09G2370/10 , H03M9/00 , H04L7/0087 , H04N7/015
Abstract: Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include a receiver circuit and one of the provided techniques includes receiving a data stream at the receiver circuit. The receiver circuit may include a detector circuit that is used to determine the data rate of the received data stream. A controller block in the receiver circuit may accordingly configure a deserializer circuit in the receiver circuit based on the data rate of the received data stream. The circuitry may further include a transmitter circuit for transmitting data streams. The transmitter circuit may be configured during runtime based on the data rate of a data stream that is being transmitted. In some instances, irrespective of the data rate of the data stream being transmitted, a constant reference clock may be used in the transmitter circuit.
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公开(公告)号：US09882708B2
公开(公告)日：2018-01-30
申请号：US15047413
申请日：2016-02-18
Applicant: Altera Corporation
Inventor： Boon Hong Oh , Chee Wai Yap
CPC classification number: H04L7/0332 , G09G5/006 , G09G2370/10 , H03M9/00 , H04L7/0087 , H04N7/015
Abstract: Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include a receiver circuit and one of the provided techniques includes receiving a data stream at the receiver circuit. The receiver circuit may include a detector circuit that is used to determine the data rate of the received data stream. A controller block in the receiver circuit may accordingly configure a deserializer circuit in the receiver circuit based on the data rate of the received data stream. The circuitry may further include a transmitter circuit for transmitting data streams. The transmitter circuit may be configured during runtime based on the data rate of a data stream that is being transmitted. In some instances, irrespective of the data rate of the data stream being transmitted, a constant reference clock may be used in the transmitter circuit.
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公开(公告)号：US20160164668A1
公开(公告)日：2016-06-09
申请号：US15047413
申请日：2016-02-18
Applicant: Altera Corporation
Inventor： Boon Hong Oh , Chee Wai Yap
CPC classification number: H04L7/0332 , G09G5/006 , G09G2370/10 , H03M9/00 , H04L7/0087 , H04N7/015
Abstract: Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include a receiver circuit and one of the provided techniques includes receiving a data stream at the receiver circuit. The receiver circuit may include a detector circuit that is used to determine the data rate of the received data stream. A controller block in the receiver circuit may accordingly configure a deserializer circuit in the receiver circuit based on the data rate of the received data stream. The circuitry may further include a transmitter circuit for transmitting data streams. The transmitter circuit may be configured during runtime based on the data rate of a data stream that is being transmitted. In some instances, irrespective of the data rate of the data stream being transmitted, a constant reference clock may be used in the transmitter circuit.
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