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公开(公告)号：US20200235906A1
公开(公告)日：2020-07-23
申请号：US16841622
申请日：2020-04-06
Applicant: Altera Corporation
Inventor： Boon Hong Oh , Chee Seng Tan , Chau Perng Chin
Abstract: Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include rate detection circuitry, receiver circuitry, and configuration circuitry. The receiver circuitry may receive a data stream with an arbitrary data rate. The rate detection circuitry may receive a reference clock signal that is associated with the received data stream. The rate detection circuitry determines the frequency of the reference clock signal such that an appropriate clock signal may be generated for the receiver circuitry. The receiver clock signal may be generated by clock generation circuitry that is coupled to the rate detection circuitry. The configuration circuitry may accordingly configure the receiver circuitry based at least on the determined frequency of the reference clock signal so that the receiver circuitry may operate at the arbitrary data rate.
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公开(公告)号：US10129013B1
公开(公告)日：2018-11-13
申请号：US15415751
申请日：2017-01-25
Applicant: Altera Corporation
Inventor： Boon Hong Oh , Chee Seng Tan , Chau Perng Chin
Abstract: Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include rate detection circuitry, receiver circuitry, and configuration circuitry. The receiver circuitry may receive a data stream with an arbitrary data rate. The rate detection circuitry may receive a reference clock signal that is associated with the received data stream. The rate detection circuitry determines the frequency of the reference clock signal such that an appropriate clock signal may be generated for the receiver circuitry. The receiver clock signal may be generated by clock generation circuitry that is coupled to the rate detection circuitry. The configuration circuitry may accordingly configure the receiver circuitry based at least on the determined frequency of the reference clock signal so that the receiver circuitry may operate at the arbitrary data rate.
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公开(公告)号：US09559834B1
公开(公告)日：2017-01-31
申请号：US14605871
申请日：2015-01-26
Applicant: Altera Corporation
Inventor： Boon Hong Oh , Chee Sent Tan , Chau Perng Chin
CPC classification number: H03L7/00
Abstract: Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include rate detection circuitry, receiver circuitry, and configuration circuitry. The receiver circuitry may receive a data stream with an arbitrary data rate. The rate detection circuitry may receive a reference clock signal that is associated with the received data stream. The rate detection circuitry determines the frequency of the reference clock signal such that an appropriate clock signal may be generated for the receiver circuitry. The receiver clock signal may be generated by clock generation circuitry that is coupled to the rate detection circuitry. The configuration circuitry may accordingly configure the receiver circuitry based at least on the determined frequency of the reference clock signal so that the receiver circuitry may operate at the arbitrary data rate.
Abstract translation: 提供了在集成电路中操作电路的技术。 电路可以包括速率检测电路，接收器电路和配置电路。 接收机电路可以接收具有任意数据速率的数据流。 速率检测电路可以接收与所接收的数据流相关联的参考时钟信号。 速率检测电路确定参考时钟信号的频率，使得可以为接收机电路产生适当的时钟信号。 接收机时钟信号可以由耦合到速率检测电路的时钟产生电路产生。 因此，配置电路可以至少基于所确定的参考时钟信号的频率来配置接收机电路，使得接收机电路可以以任意数据速率工作。
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公开(公告)号：US10958411B2
公开(公告)日：2021-03-23
申请号：US16841622
申请日：2020-04-06
Applicant: Altera Corporation
Inventor： Boon Hong Oh , Chee Seng Tan , Chau Perng Chin
Abstract: Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include rate detection circuitry, receiver circuitry, and configuration circuitry. The receiver circuitry may receive a data stream with an arbitrary data rate. The rate detection circuitry may receive a reference clock signal that is associated with the received data stream. The rate detection circuitry determines the frequency of the reference clock signal such that an appropriate clock signal may be generated for the receiver circuitry. The receiver clock signal may be generated by clock generation circuitry that is coupled to the rate detection circuitry. The configuration circuitry may accordingly configure the receiver circuitry based at least on the determined frequency of the reference clock signal so that the receiver circuitry may operate at the arbitrary data rate.
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公开(公告)号：US20190097784A1
公开(公告)日：2019-03-28
申请号：US16154513
申请日：2018-10-08
Applicant: Altera Corporation
Inventor： Boon Hong Oh , Chee Sent Tan , Chau Perng Chin
Abstract: Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include rate detection circuitry, receiver circuitry, and configuration circuitry. The receiver circuitry may receive a data stream with an arbitrary data rate. The rate detection circuitry may receive a reference clock signal that is associated with the received data stream. The rate detection circuitry determines the frequency of the reference clock signal such that an appropriate clock signal may be generated for the receiver circuitry. The receiver clock signal may be generated by clock generation circuitry that is coupled to the rate detection circuitry. The configuration circuitry may accordingly configure the receiver circuitry based at least on the determined frequency of the reference clock signal so that the receiver circuitry may operate at the arbitrary data rate.
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Patent Agency Ranking
公开(公告)号：US09300463B2
公开(公告)日：2016-03-29
申请号：US14271348
申请日：2014-05-06
Applicant: Altera Corporation
Inventor： Boon Hong Oh , Chee Wai Yap
CPC classification number: H04L7/0332 , G09G5/006 , G09G2370/10 , H03M9/00 , H04L7/0087 , H04N7/015
Abstract: Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include a receiver circuit and one of the provided techniques includes receiving a data stream at the receiver circuit. The receiver circuit may include a detector circuit that is used to determine the data rate of the received data stream. A controller block in the receiver circuit may accordingly configure a deserializer circuit in the receiver circuit based on the data rate of the received data stream. The circuitry may further include a transmitter circuit for transmitting data streams. The transmitter circuit may be configured during runtime based on the data rate of a data stream that is being transmitted. In some instances, irrespective of the data rate of the data stream being transmitted, a constant reference clock may be used in the transmitter circuit.
Abstract translation: 提供了在集成电路中操作电路的技术。 电路可以包括接收器电路，并且所提供的技术之一包括在接收器电路处接收数据流。 接收器电路可以包括用于确定接收的数据流的数据速率的检测器电路。 因此接收机电路中的控制器块可以相应地基于所接收的数据流的数据速率来配置接收机电路中的解串行电路。 电路还可以包括用于传输数据流的发射机电路。 发射机电路可以在运行期间根据正被发送的数据流的数据速率进行配置。 在一些情况下，不管发送的数据流的数据速率如何，在发射机电路中可以使用恒定的参考时钟。
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公开(公告)号：US20150288511A1
公开(公告)日：2015-10-08
申请号：US14271348
申请日：2014-05-06
Applicant: Altera Corporation
Inventor： Boon Hong Oh , Chee Wai Yap
CPC classification number: H04L7/0332 , G09G5/006 , G09G2370/10 , H03M9/00 , H04L7/0087 , H04N7/015
Abstract: Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include a receiver circuit and one of the provided techniques includes receiving a data stream at the receiver circuit. The receiver circuit may include a detector circuit that is used to determine the data rate of the received data stream. A controller block in the receiver circuit may accordingly configure a deserializer circuit in the receiver circuit based on the data rate of the received data stream. The circuitry may further include a transmitter circuit for transmitting data streams. The transmitter circuit may be configured during runtime based on the data rate of a data stream that is being transmitted. In some instances, irrespective of the data rate of the data stream being transmitted, a constant reference clock may be used in the transmitter circuit.
Abstract translation: 提供了在集成电路中操作电路的技术。 电路可以包括接收器电路，并且所提供的技术之一包括在接收器电路处接收数据流。 接收器电路可以包括用于确定接收的数据流的数据速率的检测器电路。 因此接收机电路中的控制器块可以相应地基于所接收的数据流的数据速率来配置接收机电路中的解串行电路。 电路还可以包括用于传输数据流的发射机电路。 发射机电路可以在运行期间根据正被发送的数据流的数据速率进行配置。 在一些情况下，不管发送的数据流的数据速率如何，在发射机电路中可以使用恒定的参考时钟。
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公开(公告)号：US10439795B2
公开(公告)日：2019-10-08
申请号：US15826472
申请日：2017-11-29
Applicant: Altera Corporation
Inventor： Boon Hong Oh , Chee Wai Yap
Abstract: Circuitry and methods of operation thereof for video communication are described herein. The circuitry described herein may be programmable circuitry. The circuitry may include a receiver circuit and/or a transmitter circuit and one of the provided techniques includes receiving and/or transmitting video data. The receiver circuit may include a detector circuit that is used to determine the data rate of the received video data stream. The circuitry may further include a transmitter circuit for transmitting data streams. The transmitter circuit may be configured during runtime based on the data rate of a data stream that is being transmitted. The data rate of the video data stream may be associated with a video standard. In some instances, irrespective of the data rate of the data stream being transmitted, a constant reference clock may be used in the transmitter circuit. The circuitry discussed herein can support multiple protocol data paths.
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公开(公告)号：US20180083765A1
公开(公告)日：2018-03-22
申请号：US15826472
申请日：2017-11-29
Applicant: Altera Corporation
Inventor： Boon Hong Oh , Chee Wai Yap
CPC classification number: H04L7/0332 , G09G5/006 , G09G2370/10 , H03M9/00 , H04L7/0087 , H04N7/015
Abstract: Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include a receiver circuit and one of the provided techniques includes receiving a data stream at the receiver circuit. The receiver circuit may include a detector circuit that is used to determine the data rate of the received data stream. A controller block in the receiver circuit may accordingly configure a deserializer circuit in the receiver circuit based on the data rate of the received data stream. The circuitry may further include a transmitter circuit for transmitting data streams. The transmitter circuit may be configured during runtime based on the data rate of a data stream that is being transmitted. In some instances, irrespective of the data rate of the data stream being transmitted, a constant reference clock may be used in the transmitter circuit.
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公开(公告)号：US09882708B2
公开(公告)日：2018-01-30
申请号：US15047413
申请日：2016-02-18
Applicant: Altera Corporation
Inventor： Boon Hong Oh , Chee Wai Yap
CPC classification number: H04L7/0332 , G09G5/006 , G09G2370/10 , H03M9/00 , H04L7/0087 , H04N7/015
Abstract: Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include a receiver circuit and one of the provided techniques includes receiving a data stream at the receiver circuit. The receiver circuit may include a detector circuit that is used to determine the data rate of the received data stream. A controller block in the receiver circuit may accordingly configure a deserializer circuit in the receiver circuit based on the data rate of the received data stream. The circuitry may further include a transmitter circuit for transmitting data streams. The transmitter circuit may be configured during runtime based on the data rate of a data stream that is being transmitted. In some instances, irrespective of the data rate of the data stream being transmitted, a constant reference clock may be used in the transmitter circuit.
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