公开(公告)号：US09490836B2

公开(公告)日：2016-11-08

申请号：US13661313

申请日：2012-10-26

Applicant: Altera Corporation

Inventor： David Mendel ,  Gregg W. Baeckler

IPC: H04J3/00 ,  H03M5/14

CPC classification number: H03M5/145

Abstract: An apparatus includes an encoder adapted to encode data bits for transmission via a communication link. The encoder includes a logic circuit. The logic circuit is adapted to perform a logic operation on a pattern of bits and the data bits in order to reduce a run-length of the data bits.

Abstract translation: 一种装置包括编码器，其适于编码经由通信链路进行传输的数据位。 编码器包括一个逻辑电路。 逻辑电路适于对位模式和数据位执行逻辑运算，以便减少数据位的运行长度。

公开(公告)号：US20140119388A1

公开(公告)日：2014-05-01

申请号：US13661313

申请日：2012-10-26

Applicant: Altera Corporation

Inventor： David Mendel ,  Gregg W. Baeckler

IPC: H03M7/00 ,  H04L29/00

CPC classification number: H03M5/145

Abstract: An apparatus includes an encoder adapted to encode data bits for transmission via a communication link. The encoder includes a logic circuit. The logic circuit is adapted to perform a logic operation on a pattern of bits and the data bits in order to reduce a run-length of the data bits.

Abstract translation: 一种装置包括编码器，其适于编码经由通信链路进行传输的数据位。 编码器包括一个逻辑电路。 逻辑电路适于对位模式和数据位执行逻辑运算，以便减少数据位的运行长度。

公开(公告)号：US10523224B2

公开(公告)日：2019-12-31

申请号：US16414451

申请日：2019-05-16

Applicant: Altera Corporation

Inventor： David Mendel ,  Carl Ebeling ,  Dana How ,  Mahesh Iyer

IPC: H03L7/23 ,  H03L7/089 ,  H03L7/099 ,  H03L7/093

Abstract: An integrated circuit includes a signal network and a phase detector circuit. The signal network includes an adjustable delay circuit. The adjustable delay circuit is coupled at an intersection in the signal network between branches of the signal network. The signal network generates a first signal at a first leaf node of the signal network in response to a second signal. The signal network generates a third signal at a second leaf node of the signal network in response to the second signal. The phase detector circuit compares phases of the first and third signals to generate a phase detection signal. The adjustable delay circuit adjusts a delay provided to the first signal relative to the second signal to reduce a skew between the first and third signals based on the phase detection signal indicating that the first and third signals have the skew.

公开(公告)号：US10333535B1

公开(公告)日：2019-06-25

申请号：US15278409

申请日：2016-09-28

Applicant: Altera Corporation

Inventor： David Mendel ,  Carl Ebeling ,  Dana How ,  Mahesh Iyer

IPC: H03L7/23 ,  H03L7/099 ,  H03L7/089 ,  H03L7/093

Abstract: An integrated circuit includes a signal network and a phase detector circuit. The signal network includes an adjustable delay circuit. The adjustable delay circuit is coupled at an intersection in the signal network between branches of the signal network. The signal network generates a first signal at a first leaf node of the signal network in response to a second signal. The signal network generates a third signal at a second leaf node of the signal network in response to the second signal. The phase detector circuit compares phases of the first and third signals to generate a phase detection signal. The adjustable delay circuit adjusts a delay provided to the first signal relative to the second signal to reduce a skew between the first and third signals based on the phase detection signal indicating that the first and third signals have the skew.

公开(公告)号：US20140218221A1

公开(公告)日：2014-08-07

申请号：US13759869

申请日：2013-02-05

Applicant: Altera Corporation

Inventor： Curt Wortman ,  David Mendel

IPC: H03M9/00

CPC classification number: H03M9/00 ,  H04J3/047 ,  H04J3/0608 ,  H04L7/0012 ,  H04L25/14

Abstract: Receiver circuits in serial lanes each generate a synchronous clock signal that is aligned with a master clock signal to allow synchronous transfer of data onto the master clock domain without corruption. A serial-to-parallel converter circuit in each receiver circuit converts a serial data signal into parallel data signals in response to one of the synchronous clock signals. Phase detection circuitry generates an indication of a phase shift based on a phase offset between the synchronous and master clock signals. A clock signal generation circuit provides an adjustment to a phase of the synchronous clock signal based on the indication of the phase shift. The serial-to-parallel converter circuit adjusts positions of bits indicated by the parallel data signals based on the adjustment to the phase of the synchronous clock signal.

Abstract translation: 串行通道中的接收器电路各自产生与主时钟信号对准的同步时钟信号，以允许将数据同步传输到主时钟域而不会损坏。 每个接收器电路中的串并转换器电路响应于同步时钟信号之一将串行数据信号转换为并行数据信号。 相位检测电路基于同步和主时钟信号之间的相位偏移产生相移的指示。 时钟信号发生电路基于相移的指示来提供对同步时钟信号的相位的调整。 串行到并行转换器电路基于对同步时钟信号的相位的调整来调整由并行数据信号指示的位的位置。

公开(公告)号：US09240804B2

公开(公告)日：2016-01-19

申请号：US13759869

申请日：2013-02-05

Applicant: Altera Corporation

Inventor： Curt Wortman ,  David Mendel

IPC: H04L7/00 ,  H03M9/00 ,  H04L25/14 ,  H04J3/04 ,  H04J3/06

CPC classification number: H03M9/00 ,  H04J3/047 ,  H04J3/0608 ,  H04L7/0012 ,  H04L25/14

Abstract: Receiver circuits in serial lanes each generate a synchronous clock signal that is aligned with a master clock signal to allow synchronous transfer of data onto the master clock domain without corruption. A serial-to-parallel converter circuit in each receiver circuit converts a serial data signal into parallel data signals in response to one of the synchronous clock signals. Phase detection circuitry generates an indication of a phase shift based on a phase offset between the synchronous and master clock signals. A clock signal generation circuit provides an adjustment to a phase of the synchronous clock signal based on the indication of the phase shift. The serial-to-parallel converter circuit adjusts positions of bits indicated by the parallel data signals based on the adjustment to the phase of the synchronous clock signal.

Abstract translation: 串行通道中的接收器电路各自产生与主时钟信号对准的同步时钟信号，以允许将数据同步传输到主时钟域而不会损坏。 每个接收器电路中的串并转换器电路响应于同步时钟信号之一将串行数据信号转换为并行数据信号。 相位检测电路基于同步和主时钟信号之间的相位偏移产生相移的指示。 时钟信号发生电路基于相移的指示来提供对同步时钟信号的相位的调整。 串行到并行转换器电路基于对同步时钟信号的相位的调整来调整由并行数据信号指示的位的位置。

公开(公告)号：US20190273504A1

公开(公告)日：2019-09-05

申请号：US16414451

申请日：2019-05-16

Applicant: Altera Corporation

Inventor： David Mendel ,  Carl Ebeling ,  Dana How ,  Mahesh Iyer

IPC: H03L7/23 ,  H03L7/093 ,  H03L7/099 ,  H03L7/089

Abstract: An integrated circuit includes a signal network and a phase detector circuit. The signal network includes an adjustable delay circuit. The adjustable delay circuit is coupled at an intersection in the signal network between branches of the signal network. The signal network generates a first signal at a first leaf node of the signal network in response to a second signal. The signal network generates a third signal at a second leaf node of the signal network in response to the second signal. The phase detector circuit compares phases of the first and third signals to generate a phase detection signal. The adjustable delay circuit adjusts a delay provided to the first signal relative to the second signal to reduce a skew between the first and third signals based on the phase detection signal indicating that the first and third signals have the skew.

公开(公告)号：US09531390B1

公开(公告)日：2016-12-27

申请号：US14969348

申请日：2015-12-15

Applicant: Altera Corporation

Inventor： Dong-Myung Choi ,  David Mendel

IPC: H03C1/02 ,  H03L7/07 ,  H03L7/08 ,  H03B5/08 ,  H03L7/099 ,  H04B1/16 ,  H03K5/13 ,  H03K3/03

CPC classification number: H04B1/16 ,  H03K3/0315 ,  H03K5/131 ,  H03L7/0805 ,  H03L7/099 ,  H03L7/1976 ,  H03L7/23

Abstract: An integrated circuit includes first and second data channel circuits and first and second inductor-capacitor (LC) tank oscillator circuits. The first data channel circuit generates a first data signal in response to a first clock signal. The second data channel circuit generates a second data signal in response to a second clock signal. The frequencies of the first and second clock signals are substantially the same. The first LC tank oscillator circuit generates a first periodic signal. The first clock signal is generated in response to the first periodic signal. The second LC tank oscillator circuit generates a second periodic signal. The second clock signal is generated in response to the second periodic signal. The first and second LC tank oscillator circuits generate non-overlapping frequency ranges for the first and second periodic signals.

Abstract translation: 集成电路包括第一和第二数据通道电路以及第一和第二电感 - 电容（LC）振荡电路。 第一数据信道电路响应于第一时钟信号产生第一数据信号。 第二数据通道电路响应于第二时钟信号产生第二数据信号。 第一和第二时钟信号的频率基本相同。 第一个LC槽振荡电路产生第一周期信号。 响应于第一周期信号产生第一时钟信号。 第二个LC振荡电路产生第二个周期信号。 响应于第二周期信号产生第二时钟信号。 第一和第二LC槽振荡器电路产生第一和第二周期信号的非重叠频率范围。