公开(公告)号：US20190273504A1

公开(公告)日：2019-09-05

申请号：US16414451

申请日：2019-05-16

Applicant: Altera Corporation

Inventor： David Mendel ,  Carl Ebeling ,  Dana How ,  Mahesh Iyer

IPC: H03L7/23 ,  H03L7/093 ,  H03L7/099 ,  H03L7/089

Abstract: An integrated circuit includes a signal network and a phase detector circuit. The signal network includes an adjustable delay circuit. The adjustable delay circuit is coupled at an intersection in the signal network between branches of the signal network. The signal network generates a first signal at a first leaf node of the signal network in response to a second signal. The signal network generates a third signal at a second leaf node of the signal network in response to the second signal. The phase detector circuit compares phases of the first and third signals to generate a phase detection signal. The adjustable delay circuit adjusts a delay provided to the first signal relative to the second signal to reduce a skew between the first and third signals based on the phase detection signal indicating that the first and third signals have the skew.

公开(公告)号：US10523224B2

公开(公告)日：2019-12-31

申请号：US16414451

申请日：2019-05-16

Applicant: Altera Corporation

Inventor： David Mendel ,  Carl Ebeling ,  Dana How ,  Mahesh Iyer

IPC: H03L7/23 ,  H03L7/089 ,  H03L7/099 ,  H03L7/093

Abstract: An integrated circuit includes a signal network and a phase detector circuit. The signal network includes an adjustable delay circuit. The adjustable delay circuit is coupled at an intersection in the signal network between branches of the signal network. The signal network generates a first signal at a first leaf node of the signal network in response to a second signal. The signal network generates a third signal at a second leaf node of the signal network in response to the second signal. The phase detector circuit compares phases of the first and third signals to generate a phase detection signal. The adjustable delay circuit adjusts a delay provided to the first signal relative to the second signal to reduce a skew between the first and third signals based on the phase detection signal indicating that the first and third signals have the skew.

公开(公告)号：US10333535B1

公开(公告)日：2019-06-25

申请号：US15278409

申请日：2016-09-28

Applicant: Altera Corporation

Inventor： David Mendel ,  Carl Ebeling ,  Dana How ,  Mahesh Iyer

IPC: H03L7/23 ,  H03L7/099 ,  H03L7/089 ,  H03L7/093

Abstract: An integrated circuit includes a signal network and a phase detector circuit. The signal network includes an adjustable delay circuit. The adjustable delay circuit is coupled at an intersection in the signal network between branches of the signal network. The signal network generates a first signal at a first leaf node of the signal network in response to a second signal. The signal network generates a third signal at a second leaf node of the signal network in response to the second signal. The phase detector circuit compares phases of the first and third signals to generate a phase detection signal. The adjustable delay circuit adjusts a delay provided to the first signal relative to the second signal to reduce a skew between the first and third signals based on the phase detection signal indicating that the first and third signals have the skew.

公开(公告)号：US10162924B1

公开(公告)日：2018-12-25

申请号：US15262939

申请日：2016-09-12

Applicant: Altera Corporation

Inventor： Love Singhal ,  Mahesh Iyer ,  Saurabh Adya

IPC: G06F17/50

Abstract: A method for designing a system on a target device includes identifying a candidate cluster for a node in the system based on a gain value that quantifies utility for the candidate cluster. The candidate cluster is designated as a final cluster for the node when the candidate cluster has a highest gain value among other candidate clusters for each node in the candidate cluster.