公开(公告)号：US11171652B2

公开(公告)日：2021-11-09

申请号：US16833206

申请日：2020-03-27

Applicant: Altera Corporation

Inventor： Doris Tzu Lang Chen ,  Deshanand Singh

IPC: H03K19/17756 ,  H03K19/0175

Abstract: A method of configuring a programmable integrated circuit device. A channel source within the virtual fabric is configured to receive input data from a first kernel outside of the virtual fabric and on the programmable integrated circuit device, and a channel sink within the virtual fabric is configured to transmit output data to the first kernel. The configuring of the channel source is modified such that the channel source receives input data from a second kernel in response to detecting a change in operation of the programmable integrated circuit device.

公开(公告)号：US09589090B1

公开(公告)日：2017-03-07

申请号：US14466610

申请日：2014-08-22

Applicant: Altera Corporation

Inventor： Deshanand Singh ,  Valavan Manohararajah ,  Gordon Raymond Chiu ,  Ivan Blunno ,  Stephen D. Brown

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/505 ,  G06F17/5077

Abstract: A method for designing a system on a target device includes entering the system. The system is synthesized. The system is mapped. The system is placed on the target device. The system is routed. Physical synthesis is performed on the system immediately after more than one of the entering, synthesizing, mapping, placing and routing procedures.

Abstract translation: 用于在目标设备上设计系统的方法包括进入系统。 系统合成。 系统映射。 系统放在目标设备上。 系统被路由。 在多个进入，合成，映射，放置和布线过程之后，立即在系统上进行物理合成。

公开(公告)号：US08856702B1

公开(公告)日：2014-10-07

申请号：US13935633

申请日：2013-07-05

Applicant: Altera Corporation

Inventor： Deshanand Singh ,  Valavan Manohararajah ,  Gordon Raymond Chiu ,  Ivan Blunno ,  Stephen D. Brown

IPC: G06F17/50 ,  G06F9/45 ,  G06F9/455

CPC classification number: G06F17/5054 ,  G06F17/505 ,  G06F17/5077

Abstract: A method for designing a system on a target device includes entering the system. The system is synthesized. The system is mapped. The system is placed on the target device. The system is routed. Physical synthesis is performed on the system immediately after more than one of the entering, synthesizing, mapping, placing and routing procedures.

Abstract translation: 用于在目标设备上设计系统的方法包括进入系统。 系统合成。 系统映射。 系统放在目标设备上。 系统被路由。 在多个进入，合成，映射，放置和布线过程之后，立即在系统上进行物理合成。

公开(公告)号：US10033387B2

公开(公告)日：2018-07-24

申请号：US15633291

申请日：2017-06-26

Applicant: Altera Corporation

Inventor： Doris Chen ,  Deshanand Singh

IPC: H03K19/177 ,  G06F8/41 ,  H04L12/947 ,  H04L12/933

Abstract: A method of configuring a programmable integrated circuit device to implement control flow at a current basic block. A branch selector node within the current basic block is configured to receive at least one control signal, where each of the at least one control signal is associated with a respective previous basic block. The branch selector node is further configured to select one of the at least one control signal based on one or more intended destinations for the at least one control signal, and provide the selected control signal to a data selector node within the current basic block. The data selector node is configured to select a data signal based on the selected control signal, where the selected data signal is from the respective previous basic block that is associated with the selected control signal.

公开(公告)号：US09922150B1

公开(公告)日：2018-03-20

申请号：US14538666

申请日：2014-11-11

Applicant: Altera Corporation

Inventor： Peter Yiannacouras ,  John Stuart Freeman ,  Deshanand Singh

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5045

Abstract: A method for designing a system on a target device includes describing the system in a high-level synthesis language where the system includes a configurable clock to drive the system at a specified clock frequency. A hardware description language (HDL) of the system is generated from the high-level synthesis language. An initial compilation of the HDL of the system is performed in response to the specified clock frequency. Timing analysis is performed on the system after the initial compilation of the HDL to determine a maximum frequency which the system can be driven. The configurable clock is programmed to drive the system at the maximum frequency.

公开(公告)号：US09690278B1

公开(公告)日：2017-06-27

申请号：US14249939

申请日：2014-04-10

Applicant: Altera Corporation

Inventor： Doris Chen ,  Deshanand Singh

IPC: G05B19/042 ,  H04L12/933 ,  H04L12/947

CPC classification number: H03K19/17724 ,  G05B19/0423 ,  G06F8/41 ,  H03K19/1776 ,  H04L45/38 ,  H04L45/586 ,  H04L49/10 ,  H04L49/25

Abstract: A method of configuring a programmable integrated circuit device to implement control flow at a current basic block. A branch selector node within the current basic block is configured to receive at least one control signal, where each of the at least one control signal is associated with a respective previous basic block. The branch selector node is further configured to select one of the at least one control signal based on one or more intended destinations for the at least one control signal, and provide the selected control signal to a data selector node within the current basic block. The data selector node is configured to select a data signal based on the selected control signal, where the selected data signal is from the respective previous basic block that is associated with the selected control signal.

公开(公告)号：US20160350452A1

公开(公告)日：2016-12-01

申请号：US15236949

申请日：2016-08-15

Applicant: Altera Corporation

Inventor： Doris Tzu-Lang Chen ,  Deshanand Singh

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5054 ,  G06F17/5068 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/66 ,  G06F2217/78 ,  H03K19/17736 ,  H04L41/0806 ,  H04L49/35

Abstract: A method of preparing a programmable integrated circuit device for configuration using a high-level language includes compiling a plurality of virtual programmable devices from descriptions in said high-level language. That compiling includes compiling configurations of configurable routing resources from programmable resources of said programmable integrated circuit device, and compiling configurations of a plurality of complex function blocks from programmable resources of said programmable integrated circuit device. A machine-readable data storage medium may be encoded with a library of such compiled configurations. A virtual programmable device may include a stall signal network and routing switches of the virtual programmable device may include stall signal inputs and outputs.

Abstract translation: 准备用于使用高级语言配置的可编程集成电路器件的方法包括从所述高级语言的描述中编译多个虚拟可编程器件。 该编译包括从所述可编程集成电路设备的可编程资源编译可配置路由资源的配置，以及从所述可编程集成电路设备的可编程资源编译多个复杂功能块的配置。 机器可读数据存储介质可以用这种编译配置的库进行编码。 虚拟可编程设备可以包括失速信号网络，并且虚拟可编程设备的路由交换机可以包括失速信号输入和输出。

公开(公告)号：US20150121321A1

公开(公告)日：2015-04-30

申请号：US14590367

申请日：2015-01-06

Applicant: Altera Corporation

Inventor： Doris Tzu-Lang Chen ,  Deshanand Singh

IPC: G06F17/50 ,  H04L12/931 ,  H04L12/24

CPC classification number: G06F17/505 ,  G06F17/5054 ,  G06F17/5077 ,  G06F2217/66 ,  G06F2217/78 ,  H03K19/17736 ,  H04L41/0806 ,  H04L49/35

Abstract: A method of preparing a programmable integrated circuit device for configuration using a high-level language includes compiling a plurality of virtual programmable devices from descriptions in said high-level language. the compiling includes compiling configurations of configurable routing resources from programmable resources of said programmable integrated circuit device, and compiling configurations of a plurality of complex function blocks from programmable resources of said programmable integrated circuit device. A machine-readable data storage medium may be encoded with a library of such compiled configurations. A virtual programmable device may include a stall signal network and routing switches of the virtual programmable device may include stall signal inputs and outputs.

Abstract translation: 准备用于使用高级语言配置的可编程集成电路器件的方法包括从所述高级语言的描述中编译多个虚拟可编程器件。 所述编译包括从所述可编程集成电路装置的可编程资源编译配置路由资源的配置，以及从所述可编程集成电路装置的可编程资源编译多个复杂功能块的配置。 机器可读数据存储介质可以用这种编译配置的库进行编码。 虚拟可编程设备可以包括失速信号网络，并且虚拟可编程设备的路由交换机可以包括失速信号输入和输出。

公开(公告)号：US09548740B1

公开(公告)日：2017-01-17

申请号：US14020978

申请日：2013-09-09

Applicant: Altera Corporation

Inventor： Doris Tzu-Lang Chen ,  Deshanand Singh

IPC: H03K19/177 ,  G06F17/50

CPC classification number: H03K19/17748 ,  G06F17/5054

Abstract: A method of configuring an integrated circuit device to perform a function includes storing a plurality of configurations for performing the function, each of the configurations being designed for a different characteristic of a particular input to the function. Inputs are received for the function, including the particular input. The characteristic of the particular input as received is examined, and one of the plurality of configurations is instantiated based on that characteristic of the particular input as received. A machine-readable data storage medium may be encoded with instructions to perform the method. A programmable device may be configured according to the method, and also may be incorporated into a heterogeneous system.

Abstract translation: 配置集成电路装置执行功能的方法包括存储用于执行功能的多个配置，每个配置被设计用于该功能的特定输入的不同特性。 接收到功能的输入，包括特定的输入。 检查接收到的特定输入的特性，并且基于所接收的特定输入的特性来实例化多个配置之一。 机器可读数据存储介质可以用用于执行该方法的指令进行编码。 可编程设备可以根据该方法配置，并且还可以被并入到异构系统中。

公开(公告)号：US09515658B1

公开(公告)日：2016-12-06

申请号：US14510733

申请日：2014-10-09

Applicant: Altera Corporation

Inventor： Doris Tzu Lang Chen ,  Deshanand Singh

IPC: H03K19/173 ,  H03K19/0175

CPC classification number: H03K19/017581

Abstract: A method of configuring a programmable integrated circuit device. A channel source within the virtual fabric is configured to receive input data from a first kernel outside of the virtual fabric and on the programmable integrated circuit device, and a channel sink within the virtual fabric is configured to transmit output data to the first kernel. The configuring of the channel source is modified such that the channel source receives input data from a second kernel in response to detecting a change in operation of the programmable integrated circuit device.

Abstract translation: 一种配置可编程集成电路器件的方法。 虚拟结构内的信道源被配置为从虚拟结构外部和可编程集成电路设备上的第一内核接收输入数据，并且虚拟结构内的信道宿被配置为将输出数据发送到第一内核。 修改信道源的配置，使得信道源响应于检测到可编程集成电路器件的操作变化而从第二内核接收输入数据。