公开(公告)号：US10303202B1

公开(公告)日：2019-05-28

申请号：US15236620

申请日：2016-08-15

Applicant: Altera Corporation

Inventor： Saurabh Adya ,  Mahesh A. Iyer ,  Love Singhal

IPC: G06F17/50 ,  G06F1/10 ,  G06F1/08

Abstract: A method for designing a system on a target device includes placing the system on the target device. A netlist retiming is performed on the placed system. A clock allocation and a clock region optimization are performed utilizing information from the placing and the netlist retiming.

公开(公告)号：US10162924B1

公开(公告)日：2018-12-25

申请号：US15262939

申请日：2016-09-12

Applicant: Altera Corporation

Inventor： Love Singhal ,  Mahesh Iyer ,  Saurabh Adya

IPC: G06F17/50

Abstract: A method for designing a system on a target device includes identifying a candidate cluster for a node in the system based on a gain value that quantifies utility for the candidate cluster. The candidate cluster is designated as a final cluster for the node when the candidate cluster has a highest gain value among other candidate clusters for each node in the candidate cluster.

公开(公告)号：US10242144B1

公开(公告)日：2019-03-26

申请号：US15338134

申请日：2016-10-28

Applicant: Altera Corporation

Inventor： Saurabh Adya ,  Mahesh A. Iyer ,  Love Singhal

IPC: G06F17/50

Abstract: Configuration data for an integrated circuit may be generated using logic design equipment to implement an optimal design on the integrated circuit. Implementing the optimal design may include placing hardware resources within the integrated circuit to decrease or remove overlaps between corresponding hardware resources. A given hardware resource may be defined as a rectangular region, an adjacent hardware resource may be defined as another rectangular region, and together, they may be defined as a hardware resource pair. The hardware resource pair may define an overlap region, with which a cost function may be associated. The cost function may be minimized in conjunction with other types of cost functions using a solver. The solver may generate coordinates that minimize or remove overlap to be implemented in the optimal design.

公开(公告)号：US09922157B1

公开(公告)日：2018-03-20

申请号：US14802702

申请日：2015-07-17

Applicant: Altera Corporation

Inventor： Carl Ebeling ,  Herman Henry Schmit ,  Dana How ,  Mahesh A. Iyer ,  Saurabh Adya

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5081

Abstract: A clock-tree construction method for a configurable clock grid structure having a plurality of sectors and a plurality of wire segments includes defining a clock region within the clock grid structure and constructing an H-tree that has a smallest size to cover the clock region. The method further includes aligning the clock region within the H-tree, pruning the H-tree and removing an unused segment from the H-tree. The method further includes performing a tree height reduction procedure to the pruned H-tree, and generating a clock tree with a reduced size or a reduced height from the tree height reduction procedure.