中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

6 records (took 0.013 seconds)

    Circuitry and techniques for updating configuration data in an integrated circuit
    1.
    发明授权
    Circuitry and techniques for updating configuration data in an integrated circuit 有权
    用于更新集成电路中的配置数据的电路和技术

    公开(公告)号：US09164939B2

    公开(公告)日：2015-10-20

    申请号：US14058935

    申请日：2013-10-21

    Applicant: Altera Corporation

    Inventor： Tat Mun Lui ,  Ting Lok Song

    IPC: G06F13/38 ,  H03K19/177

    CPC classification number: G06F13/385 ,  H03K19/17752 ,  H03K19/17756

    Abstract: A method of operating an integrated circuit may include receiving an update request via an input-output protocol, such as the Peripheral Interconnect Component Express (PCIe) protocol. The integrated circuit is placed in an update mode when the update request is received. State information is stored in predefined registers on the integrated circuit and configuration data on the integrated circuit may be subsequently updated. An asserted update mode signal is stored in a status register on the integrated circuit to indicate that the integrated circuit is in the update mode. The configuration data may include a core configuration portion and a peripheral configuration portion. When the integrated circuit is in the update mode, only the core configuration is updated while the peripheral configuration portion may be preserved.

    Abstract translation: 操作集成电路的方法可以包括经由诸如外围互连组件Express（PCIe）协议的输入 - 输出协议来接收更新请求。 当接收到更新请求时，集成电路处于更新模式。 状态信息存储在集成电路上的预定义寄存器中，并且可以随后更新集成电路上的配置数据。 被断言的更新模式信号被存储在集成电路的状态寄存器中，以指示集成电路处于更新模式。 配置数据可以包括核心配置部分和外围配置部分。 当集成电路处于更新模式时，只有核心配置被更新，同时可以保留外围配置部分。

    CIRCUITRY AND TECHNIQUES FOR UPDATING CONFIGURATION DATA IN AN INTEGRATED CIRCUIT
    2.
    发明申请
    CIRCUITRY AND TECHNIQUES FOR UPDATING CONFIGURATION DATA IN AN INTEGRATED CIRCUIT 有权
    用于在集成电路中更新配置数据的电路和技术

    公开(公告)号：US20150113177A1

    公开(公告)日：2015-04-23

    申请号：US14058935

    申请日：2013-10-21

    Applicant: Altera Corporation

    Inventor： Tat Mun Lui ,  Ting Lok Song

    IPC: G06F13/38

    CPC classification number: G06F13/385 ,  H03K19/17752 ,  H03K19/17756

    Abstract: A method of operating an integrated circuit may include receiving an update request via an input-Output protocol, such as the Peripheral Interconnect Component Express (PCIe) protocol. The integrated circuit is placed in an update mode when the update request is received. State information is stored in predefined registers on the integrated circuit and configuration data on the integrated circuit may be subsequently updated. An asserted update mode signal is stored in a status register on the integrated circuit to indicate that the integrated circuit is in the update mode. The configuration data may include a core configuration portion and a peripheral configuration portion. When the integrated circuit is in the update mode, only the core configuration is updated while the peripheral configuration portion may be preserved.

    Abstract translation: 操作集成电路的方法可以包括经由诸如外围互连组件Express（PCIe）协议的输入 - 输出协议来接收更新请求。 当接收到更新请求时，集成电路处于更新模式。 状态信息存储在集成电路上的预定义寄存器中，并且可以随后更新集成电路上的配置数据。 被断言的更新模式信号被存储在集成电路的状态寄存器中，以指示集成电路处于更新模式。 配置数据可以包括核心配置部分和外围配置部分。 当集成电路处于更新模式时，只有核心配置被更新，同时可以保留外围配置部分。

    Power management for PCI express
    4.
    发明授权
    Power management for PCI express 有权
    PCI Express电源管理

    公开(公告)号：US09467120B1

    公开(公告)日：2016-10-11

    申请号：US14135447

    申请日：2013-12-19

    Applicant: Altera Corporation

    Inventor： Ting Lok Song

    IPC: G06F1/26 ,  G06F1/32 ,  H03K3/012

    CPC classification number: G06F1/3237 ,  G06F1/3253 ,  H03K3/012 ,  H03K19/0016 ,  H03L7/0807 ,  H04L7/0331 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D50/20

    Abstract: Systems and methods are provided for managing power of a device coupled with a transceiver module, in communication with a high-speed interface. In one aspect, a dynamic clock trunk tree associated with the transceiver module is controlled by a trunk driver having a first clock tree gate. A dynamic clock leaf tree associated with the device is controlled by a leaf driver having a second clock tree gate. Significant power savings may be achieved, for example, by triggering activation of clock gating mechanisms.

    Abstract translation: 提供的系统和方法用于管理与高速接口通信的与收发器模块耦合的设备的功率。 在一个方面，与收发器模块相关联的动态时钟中继树由具有第一时钟树门的中继线驱动器控制。 与设备相关联的动态时钟叶树由具有第二时钟树门的叶驱动器控制。 例如，通过触发时钟门控机制的激活，可以实现显着的功率节省。

    Method and apparatus to calibrate duty cycle distortion
    5.
    发明授权
    Method and apparatus to calibrate duty cycle distortion 有权
    校准占空比失真的方法和装置

    公开(公告)号：US09237001B1

    公开(公告)日：2016-01-12

    申请号：US14159248

    申请日：2014-01-20

    Applicant: ALTERA CORPORATION

    Inventor： Ting Lok Song ,  Wai Tat Wong

    IPC: H04B3/46 ,  H04B17/00 ,  H04Q1/20 ,  H04L7/00

    CPC classification number: H04L7/0016 ,  G06F1/10 ,  H03K5/1565 ,  H03K7/08 ,  H03M9/00 ,  H04L25/03 ,  H04L25/05 ,  H04L25/14

    Abstract: One embodiment relates to a method of calibrating duty cycle distortion. A data rate of a physical layer interface is changed from a lower rate to a higher rate, and a data rate of one or more transceivers associated with the physical layer interface is changed from the lower rate to the higher rate. An electrical idle state is maintained after changing the data rate of the transceiver. Duty cycle distortion calibration for one or more transceivers associated with the physical layer interface is then performed during the electrical idle state. Other embodiments and features are also disclosed.

    Abstract translation: 一个实施例涉及校准占空比失真的方法。 物理层接口的数据速率从较低速率变化到较高速率，并且与物理层接口相关联的一个或多个收发器的数据速率从较低速率变为较高速率。 在更改收发器的数据速率后，保持电气空闲状态。 然后在电气空闲状态期间执行与物理层接口相关联的一个或多个收发器的占空比失真校准。 还公开了其它实施例和特征。

Patent Agency Ranking