公开(公告)号：US20200118880A1

公开(公告)日：2020-04-16

申请号：US16706541

申请日：2019-12-06

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01L21/822 ,  H01L21/3065 ,  B23K26/36 ,  H01L23/544 ,  H01L21/67 ,  H01J37/32 ,  H01L21/78 ,  H01L21/308

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US10566238B2

公开(公告)日：2020-02-18

申请号：US16193886

申请日：2018-11-16

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01L21/00 ,  H01L21/822 ,  H01L21/308 ,  H01L21/67 ,  H01L21/78 ,  H01J37/32 ,  H01L23/544 ,  B23K26/36 ,  H01L21/3065 ,  H01L21/683

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US20190088549A1

公开(公告)日：2019-03-21

申请号：US16193886

申请日：2018-11-16

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01L21/822 ,  H01J37/32 ,  H01L21/67 ,  H01L21/3065 ,  B23K26/36 ,  H01L23/544 ,  H01L21/78 ,  H01L21/308 ,  H01L21/683

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US12131952B2

公开(公告)日：2024-10-29

申请号：US18116736

申请日：2023-03-02

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01L21/00 ,  B23K26/36 ,  H01J37/32 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/67 ,  H01L21/78 ,  H01L21/822 ,  H01L23/544 ,  H01L21/683

CPC classification number: H01L21/822 ,  B23K26/36 ,  H01J37/32889 ,  H01J37/32899 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/67069 ,  H01L21/67207 ,  H01L21/78 ,  H01L23/544 ,  H01L21/67092 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US20200286787A1

公开(公告)日：2020-09-10

申请号：US16885142

申请日：2020-05-27

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01L21/822 ,  H01L21/308 ,  H01L21/67 ,  H01L21/78 ,  H01J37/32 ,  H01L23/544 ,  B23K26/36 ,  H01L21/3065

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US20200258780A1

公开(公告)日：2020-08-13

申请号：US16863950

申请日：2020-04-30

Applicant: Applied Materials, Inc.

Inventor： James M. Holden ,  Alexander N. Lerner ,  Ajay Kumar ,  Brad Eaton ,  Aparna Iyer

IPC: H01L21/78 ,  H01L21/677 ,  H01L21/687 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01J37/32 ,  H01L21/67 ,  H01L21/683 ,  H01L21/3065

Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a plasma etch apparatus includes a plasma etch chamber. The plasma etch chamber includes a plasma source disposed in an upper region of the plasma etch chamber, a cathode assembly disposed below the plasma source, and a support pedestal for supporting a substrate carrier below the plasma source. The plasma etch apparatus also includes a transfer chamber coupled to the plasma etch chamber. The transfer chamber includes a transfer arm for supporting a substantial portion of a dicing tape of the substrate carrier, the transfer arm configured to transfer a sample from the support pedestal following an etch singulation process.

公开(公告)号：US20230207393A1

公开(公告)日：2023-06-29

申请号：US18116736

申请日：2023-03-02

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01L21/822 ,  H01L21/308 ,  H01L21/67 ,  H01L21/78 ,  H01J37/32 ,  H01L23/544 ,  B23K26/36 ,  H01L21/3065

CPC classification number: H01L21/822 ,  B23K26/36 ,  H01J37/32889 ,  H01J37/32899 ,  H01L21/78 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/67069 ,  H01L21/67207 ,  H01L23/544 ,  H01L21/6836 ,  H01L21/67092 ,  H01L2924/0002

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US09245802B2

公开(公告)日：2016-01-26

申请号：US14476060

申请日：2014-09-03

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01L21/00 ,  H01L21/78 ,  H01L21/308 ,  H01L21/822 ,  B23K26/36 ,  H01J37/32 ,  H01L23/544 ,  H01L21/67

CPC classification number: H01L21/822 ,  B23K26/36 ,  H01J37/32889 ,  H01J37/32899 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/67069 ,  H01L21/67092 ,  H01L21/67207 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

Abstract translation: 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 一种方法包括在半导体晶片上形成掩模，该掩模包括覆盖并保护集成电路的层。 通过激光划线工艺对掩模和半导体晶片的一部分进行构图，以提供图案化掩模，并在集成电路之间部分地形成沟槽而不通过半导体晶片。 每个沟槽都有一个宽度。 通过沟槽等离子体蚀刻半导体晶片以形成对应的沟槽延伸部分并对集成电路进行分割。 每个相应的沟槽延伸部具有宽度。

公开(公告)号：US09054176B2

公开(公告)日：2015-06-09

申请号：US14023408

申请日：2013-09-10

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01L21/00 ,  H01L21/78 ,  H01L21/3065 ,  B23K26/06 ,  B23K26/36 ,  B23K26/40 ,  H01L21/67

CPC classification number: H01L21/78 ,  B23K26/0624 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/172 ,  B23K2103/42 ,  B23K2103/50 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/67207

Abstract: Methods of dicing substrates by both laser scribing and plasma etching are disclosed. A method includes laser ablating material layers, the ablating leading with a first irradiance and following with a second irradiance, lower than the first. Multiple passes of a beam adjusted to have different fluence level or multiple laser beams having various fluence levels may be utilized to ablate mask and IC layers to expose a substrate with the first fluence level and then clean off redeposited materials from the trench bottom with the second fluence level. A laser scribe apparatus employing a beam splitter may provide first and second beams of different fluence from a single laser.

Abstract translation: 公开了通过激光划线和等离子体蚀刻来切割衬底的方法。 一种方法包括激光烧蚀材料层，具有第一辐照度的烧蚀导线，并且具有低于第一辐照度的第二辐照度。 调整为具有不同注量级的光束的多次通过或具有各种注量级的多个激光束可以用于消除掩模和IC层以暴露具有第一注量级的衬底，然后用第二注入层从沟槽底部清除再沉积的材料 注量水平 使用分束器的激光划片装置可以从单个激光器提供不同注量的第一和第二光束。

公开(公告)号：US08853056B2

公开(公告)日：2014-10-07

申请号：US14146887

申请日：2014-01-03

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01L21/00 ,  H01L21/78 ,  H01L21/67 ,  H01L21/822 ,  H01L21/308

CPC classification number: H01L21/822 ,  B23K26/36 ,  H01J37/32889 ,  H01J37/32899 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/67069 ,  H01L21/67092 ,  H01L21/67207 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

Abstract translation: 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 一种方法包括在半导体晶片上形成掩模，该掩模包括覆盖并保护集成电路的层。 通过激光划线工艺对掩模和半导体晶片的一部分进行构图，以提供图案化掩模，并在集成电路之间部分地形成沟槽而不通过半导体晶片。 每个沟槽都有一个宽度。 通过沟槽等离子体蚀刻半导体晶片以形成对应的沟槽延伸部分并对集成电路进行分割。 每个相应的沟槽延伸部具有宽度。