中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

17 records (took 0.019 seconds)

    CONFIGURATIONS OF SOLID STATE THIN FILM BATTERIES
    1.
    发明申请
    CONFIGURATIONS OF SOLID STATE THIN FILM BATTERIES 审中-公开

    公开(公告)号：US20170149093A1

    公开(公告)日：2017-05-25

    申请号：US15389050

    申请日：2016-12-22

    Applicant: Applied Materials, Inc.

    Inventor： Lizhong Sun ,  Byung-Sung Leo Kwak ,  Miaojun Wang ,  Dimitrios Argyris ,  Daoying Song

    IPC: H01M10/0585 ,  H01M10/0562 ,  H01M10/42 ,  H01M10/04

    CPC classification number: H01M10/0585 ,  H01M10/0404 ,  H01M10/0436 ,  H01M10/0562

    Abstract: A solid state thin film battery may comprise: an adhesion promotion and intermixing barrier layer on a substrate, the layer comprising an electrically insulating material having a thickness in the range of 50 nm to 5,000 nm; a metal adhesion layer on the adhesion promotion and intermixing barrier layer; a current collector layer on the metal adhesion layer; a cathode layer on the current collector layer; an electrolyte layer on the cathode layer; and an anode layer on the electrolyte layer; wherein the device layers form a stack on the thin substrate; and wherein the adhesion promotion layer prevents cracking of the stack and delamination from the thin substrate of the stack during fabrication of the stack, including annealing of the cathode at a temperature in the range of 500° C. to 800° C., and/or intermixing of the current collector and cathode layers during annealing of the cathode layer.

    Selectively deposited parylene masks and methods related thereto
    5.
    发明授权
    Selectively deposited parylene masks and methods related thereto 有权

    公开(公告)号：US10714339B2

    公开(公告)日：2020-07-14

    申请号：US16246776

    申请日：2019-01-14

    Applicant: Applied Materials, Inc.

    Inventor： Fei Wang ,  Miaojun Wang ,  Pramit Manna ,  Shishi Jiang ,  Abhijit Basu Mallick ,  Robert Jan Visser

    IPC: H01L21/027 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/32 ,  H01L21/311

    Abstract: Methods of selectively depositing a mask layer on a surface of a patterned substrate and self-aligned patterned masks are provided herein. In one embodiment, a method of selectivity depositing a mask layer includes positioning the patterned substrate on a substrate support in a processing volume of a processing chamber, exposing the surface of the patterned substrate to a parylene monomer gas, forming a first layer on the patterned substrate, wherein the first layer comprises a patterned parylene layer, and depositing a second layer on the first layer. In another embodiment, a self-aligned patterned mask comprises a parylene layer comprising a plurality of parylene features and a plurality of openings, the parylene layer is disposed on a patterned substrate comprising a dielectric layer and a plurality of metal features, the plurality of metal feature comprise a parylene deposition inhibitor metal, and the plurality of parylene features are selectivity formed on dielectric surfaces of the dielectric layer.

Patent Agency Ranking