公开(公告)号：US20030219988A1

公开(公告)日：2003-11-27

申请号：US10154532

申请日：2002-05-22

Applicant: Applied Materials, Inc.

Inventor： Hongqing Shan ,  Kenny L. Doan ,  Jingbao Liu ,  Michael S. Barnes ,  Huong Thanh Nguyen ,  Christopher Dennis Bencher ,  Christopher S. Ngai ,  Wendy H. Yeh ,  Eda Tuncel ,  Claes H. Bjorkman

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L21/31144 ,  G03F7/40 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/0271 ,  H01L21/31116 ,  H01L21/312 ,  H01L21/3146

Abstract: A method is described for decreasing the critical dimensions of integrated circuit features in which a first masking layer (101) is deposited, patterned and opened in the manner of typical feature etching, and a second masking layer (201) is deposited thereon prior to etching the underlying insulator. The second masking layer is advantageously coated in a substantially conformal manner. Opening the second masking layer while leaving material of the second layer on the sidewalls of the first masking layer as spacers leads to reduction of the feature critical dimension in the underlying insulator. Ashable masking materials, including amorphous carbon and organic materials are removable without CMP, thereby reducing costs. Favorable results are also obtained utilizing more than one masking layer (101, 301) underlying the topmost masking layer (302) from which the spacers are formed. Embodiments are also described in which slope etching replaces the addition of a separate spacer layer. Substructures formed in the fabrication process are also described. Spacers are also shown to be favorably employed in making feature-in-feature structures.

Abstract translation: 描述了一种降低集成电路特征的关键尺寸的方法，其中以典型特征蚀刻的方式沉积，图案化和打开第一掩模层（101），并且在蚀刻之前沉积第二掩模层（201） 底层绝缘子。 有利地以基本上共形的方式涂覆第二掩模层。 打开第二掩蔽层，同时将第二层的材料留在第一掩模层的侧壁上作为间隔物导致下层绝缘体中的特征临界尺寸的减小。 包括无定形碳和有机材料在内的可湿性掩蔽材料可以不经CMP去除，从而降低成本。 利用形成间隔物的最上面的掩模层（302）下方的多于一个掩模层（101,301）也可获得有利的结果。 还描述了其中斜率蚀刻替代单独的间隔层的添加的实施例。 还描述了在制造过程中形成的子结构。 垫片也被用于制造特征特征结构。

公开(公告)号：US20030226641A1

公开(公告)日：2003-12-11

申请号：US10164327

申请日：2002-06-05

Applicant: Applied Materials, Inc.

Inventor： Kenneth S. Collins ,  Hiroji Hanawa ,  Yan Ye ,  Kartik Ramaswamy ,  Andrew Nguyen ,  Michael S. Barnes ,  Huong Thanh Nguyen

IPC: C23F001/00 ,  C23C016/00

CPC classification number: H01J37/321 ,  H01J37/32082 ,  H01J37/32412

Abstract: A plasma reactor is described that includes a vacuum chamber defined by an enclosure including a side wall and a workpiece support pedestal within the chamber defining a processing region overlying said pedestal. The chamber has at least a first pair of ports near opposing sides of said processing region and a first external reentrant tube is connected at respective ends thereof to the pair of ports. The reactor further includes a process gas injection apparatus (such as a gas distribution plate) and an RF power applicator coupled to the reentrant tube for applying plasma source power to process gases within the tube to produce a reentrant torroidal plasma current through the first tube and across said processing region. A magnet controls radial distribution of plasma ion density in the processing region, the magnet having an elongate pole piece defining a pole piece axis intersecting the processing region.

Abstract translation: 描述了一种等离子体反应器，其包括由壳体限定的真空室，所述外壳包括在所述腔室内的侧壁和工件支撑基座，其限定覆盖所述基座的处理区域。 所述腔室具有在所述处理区域的相对侧附近的至少第一对端口，并且第一外部可折入管的相应端部连接到所述一对端口。 反应器还包括工艺气体注入装置（例如气体分配板）和耦合到可折入管的RF功率施加器，其用于施加等离子体源功率以处理管内的气体，以产生通过第一管的可重入环形等离子体电流， 跨越所述处理区域。 磁体控制处理区域中的等离子体离子密度的径向分布，磁体具有限定与加工区域相交的极片轴线的细长极片。

公开(公告)号：US20040026368A1

公开(公告)日：2004-02-12

申请号：US10215065

申请日：2002-08-07

Applicant: Applied Materials, Inc.

Inventor： Michael S. Barnes ,  John P. Holland ,  David S.L. Mui ,  Wei Liu

IPC: C23F001/00

CPC classification number: H01J37/321 ,  C23C14/547 ,  C23C16/52 ,  G01N21/4788 ,  G01N21/9501 ,  G01N21/956 ,  H01J37/32935

Abstract: A substrate is placed in a process zone and an energized process gas is maintained in the process zone to process the substrate. A light beam is reflectively diffracted from a pattern of features of the substrate being processed, the reflected beam is monitored, and a signal is generated in relation to the monitored beam. During processing, a width of the features of the substrate can change. The generated signal is evaluated to detect the occurrence of a change in the width of the features.

Abstract translation: 将基底放置在处理区中，并且在处理区中保持通电的工艺气体以处理衬底。 光束从被处理的衬底的特征的图案反射衍射，监测反射光束，并且相对于被监视的光束产生信号。 在处理期间，衬底的特征的宽度可以改变。 评估产生的信号以检测特征宽度变化的发生。

公开(公告)号：US20030176074A1

公开(公告)日：2003-09-18

申请号：US10241653

申请日：2002-09-10

Applicant: Applied Materials, Inc.

Inventor： Alexander Paterson ,  Valentin N. Todorov ,  Jon McChesney ,  Gerhard M. Schneider ,  David Palagashvili ,  John P. Holland ,  Michael S. Barnes

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L21/67069 ,  H01J37/32082 ,  H01J37/32458

Abstract: A method and apparatus for processing wafers including a chamber defining a plurality of isolated processing regions. The isolated processing regions have an upper end and a lower end. The chamber further includes a plurality of plasma generation devices each disposed adjacent the upper end of each isolated processing region, and one of a plurality of power supplies connected to each plasma generation device. The output frequency of the plurality of power supplies are phase and/or frequency locked together. Additionally, the chamber includes a plurality of gas distribution assemblies. Each gas distribution assembly is disposed within each isolated processing region. A movable wafer support is disposed within each isolated processing region to support a wafer for plasma processing thereon. The movable wafer support includes a bias electrode coupled to a bias power supply configured to control the bombardment of plasma ions toward the movable wafer support.

Abstract translation: 一种用于处理晶片的方法和装置，包括限定多个隔离处理区域的腔室。 隔离处理区域具有上端和下端。 所述室还包括多个等离子体产生装置，每个等离子体产生装置邻近每个隔离处理区域的上端设置，并且连接到每个等离子体产生装置的多个电源中的一个。 多个电源的输出频率是相位和/或频率锁定在一起的。 另外，腔室包括多个气体分配组件。 每个气体分配组件设置在每个隔离的处理区域内。 可移动的晶片支撑件设置在每个隔离的处理区域内以支撑用于等离子体处理的晶片。 可移动晶片支撑件包括耦合到偏置电源的偏置电极，偏置电源被配置为控制等离子体离子朝向可移动晶片支撑件的轰击。

公开(公告)号：US20030037881A1

公开(公告)日：2003-02-27

申请号：US09931324

申请日：2001-08-16

Applicant: Applied Materials, Inc.

Inventor： Michael S. Barnes ,  John Holland ,  Alexander Paterson ,  Valentin Todorov ,  Farhad Moghadam

IPC: H01L021/302 ,  C23F001/00 ,  C23C016/00

CPC classification number: H01J37/3244 ,  H01J37/32082

Abstract: Apparatus and method for processing a substrate are provided. The apparatus for processing a substrate comprises: a chamber having a first electrode; a substrate support disposed in the chamber and providing a second electrode; a high frequency power source electrically connected to either the first or the second electrode; a low frequency power source electrically connected to either the first or the second electrode; and a variable impedance element connected to one or more of the electrodes. The variable impedance element may be tuned to control a self bias voltage division between the first electrode and the second electrode. Embodiments of the invention substantially reduce erosion of the electrodes, maintain process uniformity, improve precision of the etch process for forming high aspect ratio sub-quarter-micron interconnect features, and provide an increased etch rate which reduces time and costs of production of integrated circuits.

Abstract translation: 提供了用于处理基板的设备和方法。 用于处理衬底的设备包括：具有第一电极的腔室; 设置在所述室中并提供第二电极的衬底支撑件; 电连接到第一或第二电极的高频电源; 电连接到第一或第二电极的低频电源; 以及连接到一个或多个电极的可变阻抗元件。 可调谐可变阻抗元件以控制第一电极和第二电极之间的自偏压分压。 本发明的实施例大大减少电极的侵蚀，保持工艺均匀性，提高用于形成高纵横比亚微米互连特征的蚀刻工艺的精度，并提供增加的蚀刻速率，从而减少集成电路的生产时间和成本 。