公开(公告)号：USD1066440S1

公开(公告)日：2025-03-11

申请号：US29867553

申请日：2022-10-28

Applicant: Applied Materials, Inc.

Designer： Yang Li ,  Xi Cen ,  Kai Wu ,  Min-Han Lee ,  Mehran Behdjat

公开(公告)号：US20240240314A1

公开(公告)日：2024-07-18

申请号：US18402079

申请日：2024-01-02

Applicant: Applied Materials, Inc.

Inventor： Zhen Liu ,  Min-Han Lee ,  Jie Zhang ,  Yongqian Gao ,  Tsung-Han Yang ,  Rongjun Wang

IPC: C23C16/455 ,  C23C16/06 ,  C23C16/56

CPC classification number: C23C16/45525 ,  C23C16/06 ,  C23C16/56

Abstract: Embodiments of the disclosure relate to methods for metal gapfill of a logic device with lower resistivity. Specific embodiments provide integrated separate tungsten PVD processes with plasma-etch to solve the overhang issue caused by tungsten PVD and the high resistivity caused by nucleation.