公开(公告)号：US20020102842A1

公开(公告)日：2002-08-01

申请号：US10074938

申请日：2002-02-11

Applicant: Applied Materials, Inc.

Inventor： Roderick Craig Mosley ,  Hong Zhang ,  Fusen Chen ,  Ted Guo ,  Liang-Yun Chen

IPC: H01L021/44 ,  H01L021/4763

CPC classification number: H01L21/76876 ,  C23C14/568 ,  C23C16/54 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879

Abstract: The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Al layer.

公开(公告)号：US20030161943A1

公开(公告)日：2003-08-28

申请号：US10367214

申请日：2003-02-13

Applicant: Applied Materials, Inc.

Inventor： Liang-Yuh Chen ,  Ted Guo ,  Roderick Craig Mosley ,  Fusen Chen

IPC: B05D005/12 ,  C23C016/00

CPC classification number: H01L21/28562 ,  H01L21/76879

Abstract: The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates selective chemical vapor deposition aluminum (CVD Al) via fill with a metal wire, preferably copper, formed within a barrier layer. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.