公开(公告)号：US12141688B2

公开(公告)日：2024-11-12

申请号：US17380318

申请日：2021-07-20

Applicant: Applied Materials, Inc.

Inventor： Milan Pesic ,  Shruba Gangopadhyay ,  Muthukumar Kaliappan ,  Michael Haverty

IPC: G06N3/065 ,  G11C11/54 ,  G11C13/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

Abstract: A crested barrier memory device may include a first electrode, a first self-rectifying layer, and a combined barrier and active layer. The first self-rectifying layer may be between the first electrode and the active layer. A conduction band offset between the first self-rectifying layer and the combined barrier and active layer may be greater than approximately 1.5 eV. A valence band offset between the first self-rectifying layer and the combined barrier and active layer may be less than approximately −0.5 eV. The device may also include a second electrode. The active layer may be between the first self-rectifying layer and the second electrode.

公开(公告)号：US20240087881A1

公开(公告)日：2024-03-14

申请号：US17896753

申请日：2022-08-26

Applicant: Applied Materials, Inc.

Inventor： Michael Haverty ,  Shruba Gangopadhyay ,  Bo Xie ,  Yijun Liu ,  Ruitong Xiong ,  Rui Lu ,  Xiaobo Li ,  Li-Qun Xia ,  Lakmal C. Kalutarage ,  Lauren Bagby

IPC: H01L21/02 ,  C23C16/40 ,  C23C16/50 ,  C23C16/56 ,  H01J37/32

CPC classification number: H01L21/02126 ,  C23C16/401 ,  C23C16/50 ,  C23C16/56 ,  H01J37/32357 ,  H01J37/32724 ,  H01J37/32834 ,  H01L21/02208 ,  H01L21/02216 ,  H01L21/02274 ,  H01J2237/332 ,  H01L21/02348

Abstract: Embodiments include semiconductor processing methods to form low-K films on semiconductor substrates are described. The processing methods may include flowing one or more deposition precursors to a semiconductor processing system, wherein the one or more deposition precursors include a silicon-containing precursor. The silicon-containing precursor may include a carbon chain. The methods may include generating a deposition plasma from the one or more deposition precursors. The methods may include depositing a silicon-and-carbon-containing material on the substrate from plasma effluents of the deposition plasma. The silicon-and-carbon-containing material as-deposited may be characterized by a dielectric constant less than or about 3.0.

公开(公告)号：US20240087880A1

公开(公告)日：2024-03-14

申请号：US17896734

申请日：2022-08-26

Applicant: Applied Materials, Inc.

Inventor： Shruba Gangopadhyay ,  Bhaskar Jyoti Bhuyan ,  Michael Haverty ,  Bo Xie ,  Li-Qun Xia ,  Rui Lu ,  Yijun Liu ,  Ruitong Xiong ,  Xiaobo Li ,  Lakmal C. Kalutarage ,  Lauren Bagby

IPC: H01L21/02 ,  C23C16/30 ,  H01J37/32

CPC classification number: H01L21/02126 ,  C23C16/30 ,  H01J37/32357 ,  H01J37/32724 ,  H01L21/02208 ,  H01L21/02274

Abstract: Embodiments include semiconductor processing methods to form low-κ films on semiconductor substrates are described. The processing methods may include flowing one or more deposition precursors to a semiconductor processing system. The one or more deposition precursors may include a silicon-containing precursor that may be a cyclic compound. The methods may include generating a deposition plasma from the one or more deposition precursors. The methods may include depositing a silicon-and-carbon-containing material on the substrate from plasma effluents of the deposition plasma. The silicon-and-carbon-containing material as-deposited may be characterized by a dielectric constant less than or about 3.0.

公开(公告)号：US20210350219A1

公开(公告)日：2021-11-11

申请号：US17380318

申请日：2021-07-20

Applicant: Applied Materials, Inc.

Inventor： Milan Pesic ,  Shruba Gangopadhyay ,  Muthukumar Kaliappan ,  Michael Haverty

IPC: G06N3/063 ,  G11C11/54 ,  H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: A crested barrier memory device may include a first electrode, a first self- rectifying layer, and a combined barrier and active layer. The first self-rectifying layer may be between the first electrode and the active layer. A conduction band offset between the first self-rectifying layer and the combined barrier and active layer may be greater than approximately 1.5 eV. A valence band offset between the first self-rectifying layer and the combined barrier and active layer may be less than approximately −0.5 eV. The device may also include a second electrode. The active layer may be between the first self-rectifying layer and the second electrode.