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    INTEGRATED DIPOLE REGION FOR TRANSISTOR
    2.
    发明公开
    INTEGRATED DIPOLE REGION FOR TRANSISTOR 审中-公开

    公开(公告)号：US20230260791A1

    公开(公告)日：2023-08-17

    申请号：US17673905

    申请日：2022-02-17

    Applicant: Applied Materials, Inc.

    Inventor： Srinivas Gandikota ,  Yixiong Yang ,  Steven C.H. Hung ,  Tianyi Huang ,  Seshadri Ganguli

    IPC: H01L21/28 ,  H01L21/324 ,  H01L21/8238

    CPC classification number: H01L21/28088 ,  H01L21/324 ,  H01L21/28185 ,  H01L21/823807 ,  H01L21/823857

    Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which comprise an integrated dipole region to meet reduced thickness and lower thermal budget requirements. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, and a dipole region having an interfacial layer, a metal film substantially free of non-metal atoms on the interfacial layer, and a high-κ dielectric layer on the metal film. In some embodiments, the dipole region of the electronic devices comprises an interfacial layer, a high-κ dielectric layer on the interfacial layer, and a metal film on the high-κ dielectric layer. In some embodiments, the methods comprise annealing the substrate to drive particles of metal from the metal film into one or more of the interfacial layer or the high-κ dielectric layer.

    INTEGRATED DIPOLE REGION FOR TRANSISTOR
    3.
    发明申请
    INTEGRATED DIPOLE REGION FOR TRANSISTOR 有权

    公开(公告)号：US20250006499A1

    公开(公告)日：2025-01-02

    申请号：US18823999

    申请日：2024-09-04

    Applicant: Applied Materials, Inc.

    Inventor： Srinivas Gandikota ,  Yixiong Yang ,  Steven C.H. Hung ,  Tianyi Huang ,  Seshadri Ganguli

    IPC: H01L21/28 ,  H01L21/324 ,  H01L21/8238

    Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which comprise an integrated dipole region to meet reduced thickness and lower thermal budget requirements. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, and a dipole region having an interfacial layer, a metal film substantially free of non-metal atoms on the interfacial layer, and a high-κ dielectric layer on the metal film. In some embodiments, the dipole region of the electronic devices comprises an interfacial layer, a high-κ dielectric layer on the interfacial layer, and a metal film on the high-κ dielectric layer. In some embodiments, the methods comprise annealing the substrate to drive particles of metal from the metal film into one or more of the interfacial layer or the high-κ dielectric layer.

    DIPOLE FORMATION PROCESSES
    4.
    发明公开
    DIPOLE FORMATION PROCESSES 审中-公开

    公开(公告)号：US20240222195A1

    公开(公告)日：2024-07-04

    申请号：US18108719

    申请日：2023-02-13

    Applicant: Applied Materials, Inc.

    Inventor： Tianyi Huang ,  Srinivas Gandikota ,  Yixiong Yang ,  Tengzhou Ma ,  Steven C.H. Hung ,  Hsin-Jung Yu ,  Geetika Bajaj

    IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/786

    CPC classification number: H01L21/823462 ,  H01L29/42392 ,  H01L29/78696

    Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices which meet reduced thickness, lower thermal budget, and Vt requirements, and have improved device performance and reliability. Advantageously, the embodiments of the present disclosure provide methods of manufacturing electronic devices that achieve desired dipole effect without an annealing process. To achieve desired dipole effect that is “thinner” than 3 Å, embodiments of the disclosure advantageously include methods of controlling surface adsorption equilibrium and, in turn, controlling the fraction of substrate surface atomic sites that are occupied by dipole species, which is not considered to be achievable by ALD processes.

    INTEGRATED DIPOLE REGION FOR TRANSISTOR
    5.
    发明公开
    INTEGRATED DIPOLE REGION FOR TRANSISTOR 审中-公开

    公开(公告)号：US20240332008A1

    公开(公告)日：2024-10-03

    申请号：US18126583

    申请日：2023-03-27

    Applicant: Applied Materials, Inc.

    Inventor： Geetika Bajaj ,  Tianyi Huang ,  Hsin-Jung Yu ,  Yixiong Yang ,  Srinivas Gandikota ,  Chi-Chou Lin ,  Pei Hsuan Lin

    IPC: H01L21/02 ,  H01L21/28

    CPC classification number: H01L21/02321 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/28229

    Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which meet reduced thickness, lower thermal budget, and Vt requirements, and have improved device performance and reliability. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, an interfacial layer on a top surface of the channel, a high-κ dielectric layer on the interfacial layer, a dipole layer on the high-κ dielectric layer, and a capping layer on the dipole layer. In some embodiments, the dipole layer comprises a metal oxynitride (MON), such as aluminum oxynitride (AlON). In some embodiments, the methods comprise annealing the substrate to drive atoms from the dipole layer into one or more of the interfacial layer or the high-κ dielectric layer.

    MULTI-PULSE DEPOSITION PROCESSES
    6.
    发明公开
    MULTI-PULSE DEPOSITION PROCESSES 审中-公开

    公开(公告)号：US20240183033A1

    公开(公告)日：2024-06-06

    申请号：US18074197

    申请日：2022-12-02

    Applicant: Applied Materials, Inc.

    Inventor： Tianyi Huang ,  Srinivas Gandikota ,  Yixiong Yang ,  Elizabeth Mao ,  Chi-Chou Lin

    IPC: C23C16/455 ,  C23C16/34 ,  H01L21/3205 ,  H01L21/768

    CPC classification number: C23C16/45527 ,  C23C16/34 ,  H01L21/32051 ,  H01L21/76843

    Abstract: Embodiments of the present disclosure advantageously provide improved control over precursor/reactant pulse/purge time, greater growth per cycle, and higher throughput during formation of a metal-containing film on a substrate surface (including substrate surfaces having at least one feature) compared to traditional atomic layer deposition (ALD) processes. In some embodiments, forming the metal-containing film comprises exposing a substrate to a constant flow of an inert carrier gas and a co-flow of a pulse of a metal-containing precursor and a pulse of a reactant. The pulse of the metal-containing precursor and the pulse of the reactant may be interrupted by a mini purge. The metal-containing precursor and/or the reactant may be charged during the mini purge to avoid precursor/reactant depletion.

    INTEGRATED DIPOLE REGION FOR TRANSISTOR
    8.
    发明公开
    INTEGRATED DIPOLE REGION FOR TRANSISTOR 审中-公开

    公开(公告)号：US20240063064A1

    公开(公告)日：2024-02-22

    申请号：US17891923

    申请日：2022-08-19

    Applicant: Applied Materials, Inc.

    Inventor： Srinivas Gandikota ,  Yixiong Yang ,  Tianyi Huang ,  Tengzhou Ma ,  Seshadri Ganguli

    IPC: H01L21/8238 ,  H01L29/51 ,  H01L21/768 ,  H01L21/324

    CPC classification number: H01L21/823821 ,  H01L29/517 ,  H01L21/76829 ,  H01L21/324 ,  H01L21/0228

    Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which comprise a dipole region and meet reduced thickness and lower thermal budget requirements. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, an interfacial layer on a top surface of the channel, a high-κ dielectric layer on the interfacial layer, a dipole layer on the high-κ dielectric layer, and optionally, a capping layer on the dipole layer. In some embodiments, the methods comprise annealing the substrate to drive atoms from the dipole layer into one or more of the interfacial layer or the high-κ dielectric layer.

    Integrated dipole region for transistor
    9.
    发明授权
    Integrated dipole region for transistor 有权

    公开(公告)号：US12112951B2

    公开(公告)日：2024-10-08

    申请号：US17673905

    申请日：2022-02-17

    Applicant: Applied Materials, Inc.

    Inventor： Srinivas Gandikota ,  Yixiong Yang ,  Steven C. H. Hung ,  Tianyi Huang ,  Seshadri Ganguli

    IPC: H01L21/28 ,  H01L21/324 ,  H01L21/8238

    CPC classification number: H01L21/28088 ,  H01L21/28185 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823857

    Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which comprise an integrated dipole region to meet reduced thickness and lower thermal budget requirements. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, and a dipole region having an interfacial layer, a metal film substantially free of non-metal atoms on the interfacial layer, and a high-κ dielectric layer on the metal film. In some embodiments, the dipole region of the electronic devices comprises an interfacial layer, a high-κ dielectric layer on the interfacial layer, and a metal film on the high-κ dielectric layer. In some embodiments, the methods comprise annealing the substrate to drive particles of metal from the metal film into one or more of the interfacial layer or the high-κ dielectric layer.

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