公开(公告)号：US20240332008A1

公开(公告)日：2024-10-03

申请号：US18126583

申请日：2023-03-27

Applicant: Applied Materials, Inc.

Inventor： Geetika Bajaj ,  Tianyi Huang ,  Hsin-Jung Yu ,  Yixiong Yang ,  Srinivas Gandikota ,  Chi-Chou Lin ,  Pei Hsuan Lin

IPC: H01L21/02 ,  H01L21/28

CPC classification number: H01L21/02321 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/28229

Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which meet reduced thickness, lower thermal budget, and Vt requirements, and have improved device performance and reliability. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, an interfacial layer on a top surface of the channel, a high-κ dielectric layer on the interfacial layer, a dipole layer on the high-κ dielectric layer, and a capping layer on the dipole layer. In some embodiments, the dipole layer comprises a metal oxynitride (MON), such as aluminum oxynitride (AlON). In some embodiments, the methods comprise annealing the substrate to drive atoms from the dipole layer into one or more of the interfacial layer or the high-κ dielectric layer.

公开(公告)号：US20230323543A1

公开(公告)日：2023-10-12

申请号：US17714513

申请日：2022-04-06

Applicant: Applied Materials, Inc.

Inventor： Tuerxun Ailihumaer ,  Yixiong Yang ,  Annamalai Lakshmanan ,  Srinivas Gandikota ,  Yogesh Sharma ,  Pei Hsuan Lin ,  Yi Xu ,  Zhimin Qi ,  Aixi Zhang ,  Shiyu Yue ,  Yu Lei

IPC: C23C30/00 ,  C23C16/02 ,  C23C16/455 ,  C23C16/56

CPC classification number: C23C30/00 ,  C23C16/0245 ,  C23C16/45525 ,  C23C16/56

Abstract: Embodiments of the disclosure advantageously provide in situ selectively deposited molybdenum films having reduced resistivity and methods of reducing or eliminating lateral growth of a selectively deposited molybdenum layer. Additional embodiments provide integrated clean and deposition processes which improve the selectivity of in situ selectively deposited molybdenum films on features, such as a via. Further embodiments advantageously provide methods of improving uniformity and selectivity of bottom-up gap fill for vias with improved film properties.

公开(公告)号：US20240363723A1

公开(公告)日：2024-10-31

申请号：US18140850

申请日：2023-04-28

Applicant: Applied Materials, Inc.

Inventor： Srinivas Gandikota ,  Tengzhou Ma ,  Geetika Bajaj ,  Debaditya Chatterjee ,  Hsin-Jung Yu ,  Pei Hsuan Lin ,  Yixiong Yang

IPC: H01L29/51 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40

CPC classification number: H01L29/513 ,  H01L21/82385 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/401 ,  H01L29/517

Abstract: Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices that meet reduced thickness, reduced leakage, lower thermal budget, and Vt requirements (including multi-Vt), and have improved device performance and reliability. The method comprises forming a P-dipole stack and an N-dipole stack on a semiconductor substrate by: depositing an interfacial layer (e.g., silicon oxide (SiOx)) on the top surface of the channel; depositing a hafnium-containing layer comprising hafnium oxide (HfOx) and having a thickness of less than or equal to 5 Å on the interfacial layer; and depositing a dipole layer comprising lanthanum nitride (LaN) on the hafnium-containing layer.