公开(公告)号：US20130285248A1

公开(公告)日：2013-10-31

申请号：US13836807

申请日：2013-03-15

Applicant: ASIA PACIFIC MICROSYSTEMS, INC.

Inventor： Hung-Lin Yin ,  Jerwei Hsieh ,  Li-Yuan Lin

IPC: H01L23/498 ,  H01L21/762

CPC classification number: H01L23/49866 ,  B81C1/00269 ,  B81C2203/019 ,  H01L21/50 ,  H01L21/76251 ,  H01L23/10 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11614 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/2745 ,  H01L2224/27462 ,  H01L2224/2747 ,  H01L2224/27614 ,  H01L2224/29011 ,  H01L2224/2908 ,  H01L2224/29082 ,  H01L2224/29084 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/32146 ,  H01L2224/32148 ,  H01L2224/32235 ,  H01L2224/32238 ,  H01L2224/32503 ,  H01L2224/32507 ,  H01L2224/48091 ,  H01L2224/48148 ,  H01L2224/48228 ,  H01L2224/48463 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73215 ,  H01L2224/81011 ,  H01L2224/81013 ,  H01L2224/81022 ,  H01L2224/81121 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81825 ,  H01L2224/81948 ,  H01L2224/83011 ,  H01L2224/83013 ,  H01L2224/83022 ,  H01L2224/83121 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83805 ,  H01L2224/83825 ,  H01L2224/83948 ,  H01L2224/9202 ,  H01L2224/92147 ,  H01L2224/95 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/16235 ,  H01L2924/351 ,  H01L2924/00015 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A substrate bonding method comprises the following steps. Firstly, a first substrate and a second substrate are provided, wherein a surface of the first substrate is covered by a first Ag layer and a surface of the second substrate is covered by a second Ag layer and a metallic layer from bottom to top, wherein the metallic layer comprises a first Sn layer. Secondly, a bonding process is performed by aligning the first and second substrates followed by bringing the metallic layer into contact with the first Ag layer followed by applying a load while heating to a predetermined temperature in order to form Ag3Sn intermetallic compounds. Finally, cool down and remove the load to complete the bonding process.

Abstract translation: 基板接合方法包括以下步骤。 首先，提供第一基板和第二基板，其中第一基板的表面被第一Ag层覆盖，并且第二基板的表面被从第二Ag层和从底部到顶部的金属层覆盖，其中 金属层包括第一Sn层。 其次，通过使第一和第二基板对准，然后使金属层与第一Ag层接触，然后在加热至预定温度的同时施加负载以形成Ag 3 Sn金属间化合物，进行接合工艺。 最后，冷却并清除负载以完成粘合过程。

公开(公告)号：US09553055B2

公开(公告)日：2017-01-24

申请号：US14922334

申请日：2015-10-26

Applicant: Asia Pacific Microsystems, Inc.

Inventor： Hung-Lin Yin

IPC: H01L23/00 ,  H01L21/283 ,  H01L21/762 ,  B06B1/02 ,  H01L21/306

CPC classification number: H01L23/562 ,  B06B1/0292 ,  B81C1/00 ,  H01L21/283 ,  H01L21/306 ,  H01L21/762 ,  H01L21/76251 ,  H01L23/00 ,  H01L24/03 ,  H01L24/84 ,  H01L24/95 ,  H01L2224/37599 ,  H01L2224/95 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/37099

Abstract: The present disclosure provides a method for fabricating semiconductor devices having reinforcing elements. The method includes steps of providing a first wafer having a lower electrode layer and an insulation layer; forming a device layer; etching the device layer and the insulation layer to form recesses; etching the device layer to form separation trenches and upper electrodes; forming reinforcing elements; and depositing metal pads. The reinforcing elements strengthen the integration of the upper electrodes and the insulation layer.

Abstract translation: 本公开提供了一种制造具有增强元件的半导体器件的方法。 该方法包括提供具有下电极层和绝缘层的第一晶片的步骤; 形成器件层; 蚀刻器件层和绝缘层以形成凹陷; 蚀刻器件层以形成分离沟槽和上电极; 形成增强元件; 并沉积金属垫。 增强元件加强了上电极和绝缘层的集成。

公开(公告)号：US20160240490A1

公开(公告)日：2016-08-18

申请号：US14922334

申请日：2015-10-26

Applicant: Asia Pacific Microsystems, Inc.

Inventor： Hung-Lin Yin

IPC: H01L23/00 ,  H01L21/762 ,  H01L21/31 ,  H01L21/311 ,  H01L21/306 ,  H01L21/283

CPC classification number: H01L23/562 ,  B06B1/0292 ,  B81C1/00 ,  H01L21/283 ,  H01L21/306 ,  H01L21/762 ,  H01L21/76251 ,  H01L23/00 ,  H01L24/03 ,  H01L24/84 ,  H01L24/95 ,  H01L2224/37599 ,  H01L2224/95 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/37099

Abstract: The present disclosure provides a method for fabricating semiconductor devices having reinforcing elements. The method includes steps of providing a first wafer having a lower electrode layer and an insulation layer; forming a device layer; etching the device layer and the insulation layer to form recesses; etching the device layer to form separation trenches and upper electrodes; forming reinforcing elements; and depositing metal pads. The reinforcing elements strengthen the integration of the upper electrodes and the insulation layer.

Abstract translation: 本公开提供了一种制造具有增强元件的半导体器件的方法。 该方法包括提供具有下电极层和绝缘层的第一晶片的步骤; 形成器件层; 蚀刻器件层和绝缘层以形成凹陷; 蚀刻器件层以形成分离沟槽和上电极; 形成增强元件; 并沉积金属垫。 增强元件加强了上电极和绝缘层的集成。

公开(公告)号：US10156489B2

公开(公告)日：2018-12-18

申请号：US15414956

申请日：2017-01-25

Applicant: Asia Pacific Microsystems, Inc.

Inventor： Hung-Lin Yin ,  Cheng-Yi Chiang ,  Yu-Che Huang

IPC: G01L9/00 ,  G01L9/06

Abstract: A piezoresistive pressure sensor includes a substrate and a silicon device layer. The substrate has a cavity. The silicon device layer includes a diaphragm and a support element. A top surface of the diaphragm is connected to a top surface of the support element by one or more side surfaces. A recess of the silicon device layer is defined by the top surface of the diaphragm and the one or more side surfaces. A plurality of piezoresistive regions are on the top surface of the diaphragm, on the one or more side surfaces and on the top surface of the support element. A plurality of conductive regions are on the top surface of the support element. The plurality of conductive regions do not extend to the top surface of the diaphragm. The plurality of piezoresistive regions have a first ion dosage concentration. The plurality of conductive regions have a second ion dosage concentration. The second ion dosage concentration is greater than the first ion dosage concentration.

公开(公告)号：US20170219449A1

公开(公告)日：2017-08-03

申请号：US15414956

申请日：2017-01-25

Applicant: Asia Pacific Microsystems, Inc.

Inventor： Hung-Lin Yin ,  Cheng-Yi Chiang ,  Yu-Che Huang

IPC: G01L9/00 ,  G01L9/06

CPC classification number: G01L9/0044 ,  G01L9/0047 ,  G01L9/0055 ,  G01L9/06

Abstract: A piezoresistive pressure sensor includes a substrate and a silicon device layer. The substrate has a cavity. The silicon device layer includes a diaphragm and a support element. A top surface of the diaphragm is connected to a top surface of the support element by one or more side surfaces. A recess of the silicon device layer is defined by the top surface of the diaphragm and the one or more side surfaces. A plurality of piezoresistive regions are on the top surface of the diaphragm, on the one or more side surfaces and on the top surface of the support element. A plurality of conductive regions are on the top surface of the support element. The plurality of conductive regions do not extend to the top surface of the diaphragm. The plurality of piezoresistive regions have a first ion dosage concentration. The plurality of conductive regions have a second ion dosage concentration. The second ion dosage concentration is greater than the first ion dosage concentration.

公开(公告)号：US20150279664A1

公开(公告)日：2015-10-01

申请号：US14670875

申请日：2015-03-27

Applicant: Asia Pacific Microsystems, Inc.

Inventor： Hung-Lin Yin

IPC: H01L21/02 ,  H01L21/461 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L21/02255 ,  B81C1/00047 ,  B81C2201/019 ,  H01L21/02554 ,  H01L21/187 ,  H01L21/461 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/80 ,  H01L24/92 ,  H01L2224/0355 ,  H01L2224/05551 ,  H01L2224/05638 ,  H01L2224/05686 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/80006 ,  H01L2224/80013 ,  H01L2224/80894 ,  H01L2224/80896 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2924/01014 ,  H01L2924/05442 ,  H01L2924/00012 ,  H01L2224/80 ,  H01L2221/68381 ,  H01L21/306 ,  H01L2224/03

Abstract: The present disclosure provides a method for fabricating semiconductor devices having high-precision gaps. The method includes steps of providing a first wafer; forming two or more regions having various ion dosage concentrations on a first surface of the first wafer; thermally oxidizing the first wafer so as to grow oxide layers with various thicknesses on the first surface of the first wafer; and bonding a second wafer to the thickest oxide layer of the first wafer so as to form one or more gaps.

Abstract translation: 本公开提供了一种制造具有高精度间隙的半导体器件的方法。 该方法包括提供第一晶片的步骤; 在所述第一晶片的第一表面上形成具有各种离子剂量浓度的两个或更多个区域; 热氧化第一晶片以在第一晶片的第一表面上生长具有各种厚度的氧化物层; 以及将第二晶片接合到所述第一晶片的最厚氧化物层，以形成一个或多个间隙。

公开(公告)号：US08916449B2

公开(公告)日：2014-12-23

申请号：US13836807

申请日：2013-03-15

Applicant: Asia Pacific Microsystems, Inc.

Inventor： Hung-Lin Yin ,  Jerwei Hsieh ,  Li-Yuan Lin

IPC: H01L21/30 ,  H01L21/46 ,  H01L23/498 ,  H01L21/762 ,  H01L23/10 ,  H01L21/50 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  B81C1/00

CPC classification number: H01L23/49866 ,  B81C1/00269 ,  B81C2203/019 ,  H01L21/50 ,  H01L21/76251 ,  H01L23/10 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11614 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/2745 ,  H01L2224/27462 ,  H01L2224/2747 ,  H01L2224/27614 ,  H01L2224/29011 ,  H01L2224/2908 ,  H01L2224/29082 ,  H01L2224/29084 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/32146 ,  H01L2224/32148 ,  H01L2224/32235 ,  H01L2224/32238 ,  H01L2224/32503 ,  H01L2224/32507 ,  H01L2224/48091 ,  H01L2224/48148 ,  H01L2224/48228 ,  H01L2224/48463 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73215 ,  H01L2224/81011 ,  H01L2224/81013 ,  H01L2224/81022 ,  H01L2224/81121 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81825 ,  H01L2224/81948 ,  H01L2224/83011 ,  H01L2224/83013 ,  H01L2224/83022 ,  H01L2224/83121 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83805 ,  H01L2224/83825 ,  H01L2224/83948 ,  H01L2224/9202 ,  H01L2224/92147 ,  H01L2224/95 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/16235 ,  H01L2924/351 ,  H01L2924/00015 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A substrate bonding method comprises the following steps. Firstly, a first substrate and a second substrate are provided, wherein a surface of the first substrate is covered by a first Ag layer and a surface of the second substrate is covered by a second Ag layer and a metallic layer from bottom to top, wherein the metallic layer comprises a first Sn layer. Secondly, a bonding process is performed by aligning the first and second substrates followed by bringing the metallic layer into contact with the first Ag layer followed by applying a load while heating to a predetermined temperature in order to form Ag3Sn intermetallic compounds. Finally, cool down and remove the load to complete the bonding process.

Abstract translation: 基板接合方法包括以下步骤。 首先，提供第一基板和第二基板，其中第一基板的表面被第一Ag层覆盖，并且第二基板的表面被从第二Ag层和从底部到顶部的金属层覆盖，其中 金属层包括第一Sn层。 其次，通过使第一和第二基板对准，然后使金属层与第一Ag层接触，然后在加热至预定温度的同时施加负载以形成Ag 3 Sn金属间化合物，进行接合工艺。 最后，冷却并清除负载以完成粘合过程。

公开(公告)号：US20130205899A1

公开(公告)日：2013-08-15

申请号：US13764780

申请日：2013-02-11

Applicant: Asia Pacific Microsystems, Inc.

Inventor： Chang-Wen Wu ,  Jerwei Hsieh ,  Wu-Chen Yeh ,  Hung-Lin Yin ,  Huai-Wei Hsi

IPC: G01P1/00

CPC classification number: G01P1/00 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0264 ,  B81B2201/0278 ,  G01P15/0802 ,  G01P15/123

Abstract: A combo transducer includes a base, a proof mass, a membrane unit and a plurality of transducing components. The base is formed with an aperture. The proof mass is disposed in the aperture and has a surface that is formed with a cavity. The membrane unit includes a supporting part connected to the base, a covering part disposed to cover the surface of the proof mass, and a resilient linking part interconnecting the supporting part and the covering part such that the proof mass is movable relative to the base. The transducing components are disposed at the membrane unit. At least one of the transducing components is disposed at the covering part and is registered with the cavity.

Abstract translation: 组合传感器包括基座，检测质量块，膜单元和多个换能元件。 基座形成有孔。 检测体设置在孔中，并具有形成有空腔的表面。 膜单元包括连接到基座的支撑部分，设置成覆盖防弹块表面的覆盖部分和将支撑部分和覆盖部分互连的弹性连接部分，使得证明物质可相对于基部移动。 传感组件设置在膜单元处。 至少一个转换部件设置在覆盖部分并且与空腔配准。