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    Silicon alignment pins: an easy way to realize a wafer-to-wafer alignment
    4.
    发明授权
    Silicon alignment pins: an easy way to realize a wafer-to-wafer alignment 有权
    硅对准引脚：实现晶片到晶片对准的简单方法

    公开(公告)号：US09512863B2

    公开(公告)日：2016-12-06

    申请号：US13871830

    申请日：2013-04-26

    Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGY

    Inventor： Cecile Jung-Kubiak ,  Theodore Reck ,  Bertrand Thomas ,  Robert H. Lin ,  Alejandro Peralta ,  John J. Gill ,  Choonsup Lee ,  Jose V. Siles ,  Risaku Toda ,  Goutam Chattopadhyay ,  Ken B. Cooper ,  Imran Mehdi

    IPC: B25G3/00 ,  F16C11/06 ,  F16D1/00 ,  F16G11/00 ,  F16B5/02

    CPC classification number: F16B5/025 ,  F16B19/004 ,  H05K13/0015 ,  Y10T29/49778 ,  Y10T29/49895 ,  Y10T403/20

    Abstract: A silicon alignment pin is used to align successive layers of components made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.

    Abstract translation: 硅对准销用于对准在半导体芯片和/或金属部件中制造的部件的连续层，以使得具有层状结构的装置的组装更容易。 该销被制成可压缩的结构，其可以被挤压以减小其外径，将一端装配到限定在待组装成层状结构的材料层中的对应的对准袋或空腔中，然后允许膨胀以产生 与空腔的过盈配合。 然后可以将另一端插入限定在与第一层配合的第二材料层的表面中的相应的空腔中。 当引脚与两者配对时，两个层都在注册表中。 可以组装多层以创建多层结构。 呈现这种装置的示例。

    ON-CHIP DIPLEXED MULTI-BAND SUBMILLIMETER-WAVE/TERAHERTZ SOURCES
    5.
    发明申请
    ON-CHIP DIPLEXED MULTI-BAND SUBMILLIMETER-WAVE/TERAHERTZ SOURCES 有权

    公开(公告)号：US20210218368A1

    公开(公告)日：2021-07-15

    申请号：US17093305

    申请日：2020-11-09

    Applicant: California Institute of Technology

    Inventor： Jose Vicente Siles Perez ,  Choonsup Lee ,  Robert H. Lin ,  Alejandro Peralta

    IPC: H03B19/18 ,  H01L23/66 ,  H01L29/872

    Abstract: A solid-state device chip including diodes (generating a higher or lower frequency output through frequency multiplication or mixing of the input frequency) and a novel on-chip diplexing design that allows combination of two or more multiplier or mixer structures operating at different frequency bands within the 50-5000 GHz range within a same chip and/or waveguide. The on-chip diplexing design consists of a single-substrate multiplier chip with two or more multiplying structures each one containing 2 or more Schottky diodes. The diodes in each structure are tuned to one portion of the target frequency band, resulting in the two or more structures working together as a whole as a large broadband multiplier or mixer. Thus, an increase in bandwidth from 10-15% (current state-of-the-art) to at least 40% is achieved. Depending on the target frequencies, each subset of diodes within the chip can be designed to work either as a doubler or a tripler.

    On-chip diplexed multi-band submillimeter-wave/terahertz sources
    10.
    发明授权
    On-chip diplexed multi-band submillimeter-wave/terahertz sources 有权

    公开(公告)号：US12087867B2

    公开(公告)日：2024-09-10

    申请号：US17093305

    申请日：2020-11-09

    Applicant: California Institute of Technology

    Inventor： Jose Vicente Siles Perez ,  Choonsup Lee ,  Robert H. Lin ,  Alejandro Peralta

    IPC: H01L29/872 ,  H01L23/66 ,  H03B19/06

    CPC classification number: H01L29/872 ,  H01L23/66 ,  H03B19/06 ,  H01L2223/6627 ,  H01L2223/6688

    Abstract: A solid-state device chip including diodes (generating a higher or lower frequency output through frequency multiplication or mixing of the input frequency) and a novel on-chip diplexing design that allows combination of two or more multiplier or mixer structures operating at different frequency bands within the 50-5000 GHz range within a same chip and/or waveguide. The on-chip diplexing design consists of a single-substrate multiplier chip with two or more multiplying structures each one containing 2 or more Schottky diodes. The diodes in each structure are tuned to one portion of the target frequency band, resulting in the two or more structures working together as a whole as a large broadband multiplier or mixer. Thus, an increase in bandwidth from 10-15% (current state-of-the-art) to at least 40% is achieved. Depending on the target frequencies, each subset of diodes within the chip can be designed to work either as a doubler or a tripler.

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