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公开(公告)号：US10755913B2
公开(公告)日：2020-08-25
申请号：US15935312
申请日：2018-03-26
Applicant: Duke University
Inventor： Jungsang Kim , Kai Hudek , Geert Vrijsen , Robert Spivey , Peter Maunz
Abstract: A package-level, integrated high-vacuum ion-chip enclosure having improved thermal characteristics is disclosed. Enclosures in accordance with the present invention include first and second chambers that are located on opposite sides of a chip carrier, where the chambers are fluidically coupled via a conduit through the chip carrier. The ion trap is located in the first chamber and disposed on the chip carrier. A source for generating an atomic flux is located in the second chamber. The separation of the source and ion trap in different chambers affords thermal isolation between them, while the conduit between the chambers enables the ion trap to receive the atomic flux.
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公开(公告)号：US11749518B2
公开(公告)日：2023-09-05
申请号：US16913932
申请日：2020-06-26
Applicant: Duke University
Inventor： Jungsang Kim , Kai Hudek , Geert Vrijsen , Robert Spivey , Peter Maunz
CPC classification number: H01J49/422 , G06N10/00 , H01J49/16 , H01J49/24 , H01J49/42
Abstract: A package-level, integrated high-vacuum ion-chip enclosure having improved thermal characteristics is disclosed. Enclosures in accordance with the present invention include first and second chambers that are located on opposite sides of a chip carrier, where the chambers are fluidically coupled via a conduit through the chip carrier. The ion trap is located in the first chamber and disposed on the chip carrier. A source for generating an atomic flux is located in the second chamber. The separation of the source and ion trap in different chambers affords thermal isolation between them, while the conduit between the chambers enables the ion trap to receive the atomic flux.
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公开(公告)号：US12142473B2
公开(公告)日：2024-11-12
申请号：US18223246
申请日：2023-07-18
Applicant: Duke University
Inventor： Jungsang Kim , Kai Hudek , Geert Vrijsen , Robert Spivey , Peter Maunz
Abstract: A package-level, integrated high-vacuum ion-chip enclosure having improved thermal characteristics is disclosed. Enclosures in accordance with the present invention include first and second chambers that are located on opposite sides of a chip carrier, where the chambers are fluidically coupled via a conduit through the chip carrier. The ion trap is located in the first chamber and disposed on the chip carrier. A source for generating an atomic flux is located in the second chamber. The separation of the source and ion trap in different chambers affords thermal isolation between them, while the conduit between the chambers enables the ion trap to receive the atomic flux.
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公开(公告)号：US10510523B2
公开(公告)日：2019-12-17
申请号：US16037988
申请日：2018-07-17
Applicant: Duke University
Inventor： Jungsang Kim , Andre Van Rynbach , Peter Maunz
Abstract: An ion-trap system having a trapping location that is controllable with nanometer-scale precision in three dimensions is disclosed. The ion-trap system includes an ion trap that includes a pair of RF driver electrodes, a pair of tuning electrodes operably coupled with the RF driver electrodes to collectively generate an RF field having an RF null that defines the trapping location, as well as a plurality of DC electrodes that are operably coupled with the RF driver electrodes and the tuning electrodes. Each tuning electrode is driven with an RF signal whose amplitude and phase is independently controllable. By controlling the amplitudes of the RF signals applied to the tuning electrodes, the height of the trapping location above the mirror is controlled. The position of the tuning location along two orthogonal lateral directions is controlled by controlling a plurality of DC voltages applied to the plurality of DC electrode pads.
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