公开(公告)号：US10192798B2

公开(公告)日：2019-01-29

申请号：US15678186

申请日：2017-08-16

Applicant: EM Microelectronic-Marin SA

Inventor： Christoph Kuratli ,  Yves Dupraz

IPC: H01L23/00 ,  H01L21/66 ,  H01L23/31 ,  H01L23/528 ,  G01R31/317 ,  G01R31/3193 ,  H01L23/525

Abstract: An electronic system is provided, including an integrated circuit die having at least 2 bond pads, and a redistribution layer having at least one solder pad including 2 portions separated from each other and configured to provide an electrical connection between each of the 2 portions by a solder ball disposed on the solder pad, and to electrically isolate the 2 portions in an absence of the solder ball on the solder pad, and at least 2 redistribution wires, each connecting a different one of the portions to a different one of the bond pads, a second bond pad being connected via a second redistribution wire to a second portion being dedicated to die testing; and a grounded printed circuit board track, wherein the solder ball is disposed between the solder pad and the track, and neither of the redistribution wires traverses a separation space between the 2 portions.

公开(公告)号：US20180053699A1

公开(公告)日：2018-02-22

申请号：US15678186

申请日：2017-08-16

Applicant: EM Microelectronic-Marin SA

Inventor： Christoph KURATLI ,  Yves Dupraz

IPC: H01L21/66 ,  H01L23/00

CPC classification number: H01L24/09 ,  G01R31/31715 ,  G01R31/31937 ,  H01L22/32 ,  H01L23/3114 ,  H01L23/525 ,  H01L23/528 ,  H01L23/5286 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05015 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06167 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/16106 ,  H01L2224/1613 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2924/014

Abstract: The invention relates to an electronic system comprising: an integrated circuit die having: at least 2 bond pads a redistribution layer, said redistribution layer having: at least a solder pad comprising 2 portions arranged to enable an electrical connection between each other by a same solder ball placed on said solder pad, but electrically isolated of each other in the absence of a solder ball on the solder pad at least 2 redistribution wires, each one connecting one of the 2 portions to one of the 2 bond pads, a second bond pad connected via a second redistribution wire to a second portion of the solder pad being dedicated to testing said integrated circuit die a grounded printed circuit board track, a solder ball being placed between the solder pad and the printed circuit board track.

公开(公告)号：US10096561B2

公开(公告)日：2018-10-09

申请号：US15678201

申请日：2017-08-16

Applicant: EM Microelectronic-Marin SA

Inventor： Christoph Kuratli ,  Yves Dupraz

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/31

Abstract: An integrated circuit die having at least two bond pads, a redistribution layer, the redistribution layer including at least one solder pad including comprising two portions arranged to enable an electrical connection between each other by a same solder ball placed on the solder pad, but electrically isolated of each other in the absence of a solder ball on the solder pad at least two redistribution wires, each one connecting one of the two portions to one of the two bond pads, a first bond pad connected via a first redistribution wire to a first portion of the solder pad being dedicated to digital ground and a second bond pad connected via a second redistribution wire to a second portion of the solder pad being dedicated to analog ground.

公开(公告)号：US20240088066A1

公开(公告)日：2024-03-14

申请号：US18463771

申请日：2023-09-08

Applicant: EM Microelectronic-Marin SA

Inventor： Christophe ENTRINGER ,  Yves Dupraz ,  Pierre Muller ,  Zeng Wang ,  Alexis Durand ,  Arthur Hugh MacDougall

IPC: H01L23/58 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L23/585 ,  H01L21/78 ,  H01L23/3192 ,  H01L24/13

Abstract: A semiconductor wafer (1a, 1b) including a plurality of chips (2) and a separation zone (3) spacing the semiconductor chips (2) from each other in this wafer (1a, 1b), such a separation zone (3) extending from a front face (4a) to an opposite backside face (4b) of this wafer (1a, 1b), this separation zone (3) includes a scribe line (6) configured to be diced using plasma etching and an inlet area (13) of this scribe line (6), the inlet (13) being delimitated by free ends of plasma etch-resistant material layers (9) extending each from a peripheral wall (20) of a functional part (18) of a chip (2) into the scribe line (6) by overlapping a top of a seal ring (7) of this chip (2).

公开(公告)号：US20230206022A1

公开(公告)日：2023-06-29

申请号：US18085770

申请日：2022-12-21

Applicant: EM Microelectronic-Marin SA

Inventor： Pierre MULLER ,  Yves Dupraz ,  Alexis Durand ,  Gordon Limond

IPC: G06K19/077

CPC classification number: G06K19/07798

Abstract: A tamper-evident RFID Tag (100) and a method for manufacturing it. The method (500) may provide (510) at least one protection layer (151) before being cured (520) such as to turn the at least one protection layer (151) into at least one degradable layer (155), and to prevent an assembly or a reassembly of the tamper-evident RFID Tag (100) after any attempt of harvesting of the tamper-evident RFID Tag (100).