公开(公告)号：US20180233216A1

公开(公告)日：2018-08-16

申请号：US15920677

申请日：2018-03-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： John A. FIFIELD ,  Eric D. HUNT-SCHROEDER ,  Darren L. ANAND

IPC: G11C29/00 ,  G11C17/16 ,  G11C17/18

CPC classification number: G11C29/78 ,  G11C17/16 ,  G11C17/18 ,  G11C29/50 ,  G11C29/50008 ,  G11C29/822 ,  G11C2029/5002 ,  G11C2029/5006

Abstract: The present disclosure relates to a structure which includes a twin-cell memory which is configured to program a plurality of write operations, a current sense amplifier which is connected to the twin-cell memory and is configured to sense a current differential and latch a differential voltage based on the current differential, and at least one current source which is connected to the current sense amplifier and is configured to add an offset current to the current sense amplifier to create the differential voltage.

公开(公告)号：US20180158532A1

公开(公告)日：2018-06-07

申请号：US15367815

申请日：2016-12-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Eric D. HUNT-SCHROEDER ,  Steven LAMPHIER ,  Darren L. ANAND

IPC: G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C17/16

Abstract: The present disclosure relates to a method of a non-volatile one time programmable memory (OTPM) including parallel programming of all banks of the OTPM by programming two rows per bank at a time, verifying the programming by comparing a first row of the two rows per bank, and verifying the programming by comparing a second row of the two rows per bank.

公开(公告)号：US20200035295A1

公开(公告)日：2020-01-30

申请号：US16047529

申请日：2018-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Faraz KHAN ,  Norman W. ROBSON ,  Toshiaki KIRIHATA ,  Danny MOY ,  Darren L. ANAND

IPC: G11C11/56 ,  H01L29/792 ,  H01L27/11573 ,  G11C16/14 ,  H01L29/73 ,  G11C16/10 ,  G11C16/04

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to program and erase memory structures and methods of manufacture. The semiconductor memory includes: a charge trap transistor; and a self-heating circuit which selectively applies voltages to terminals of the charge trap transistor to assist in erase operations of the charge trap transistor.

公开(公告)号：US20190108894A1

公开(公告)日：2019-04-11

申请号：US15730078

申请日：2017-10-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： John A. FIFIELD ,  Eric D. HUNT-SCHROEDER ,  Darren L. ANAND

IPC: G11C29/50 ,  H01L27/11517 ,  G11C16/04

CPC classification number: G11C29/50004 ,  G11C16/0408 ,  G11C16/0441 ,  G11C16/10 ,  G11C2029/5004 ,  H01L27/11517

Abstract: The present disclosure relates to a structure which includes a twin-cell memory which includes a first device and a second device and which is configured to store data which corresponds to a threshold voltage difference between the first device controlled by a first wordline and the second device controlled by a second wordline.

公开(公告)号：US20170365302A1

公开(公告)日：2017-12-21

申请号：US15695457

申请日：2017-09-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Darren L. ANAND ,  John A. FIFIELD ,  Eric D. HUNT-SCHROEDER ,  Mark D. JACUNSKI

IPC: G11C7/06 ,  G11C17/18

Abstract: A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.