公开(公告)号：US20180233216A1

公开(公告)日：2018-08-16

申请号：US15920677

申请日：2018-03-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： John A. FIFIELD ,  Eric D. HUNT-SCHROEDER ,  Darren L. ANAND

IPC: G11C29/00 ,  G11C17/16 ,  G11C17/18

CPC classification number: G11C29/78 ,  G11C17/16 ,  G11C17/18 ,  G11C29/50 ,  G11C29/50008 ,  G11C29/822 ,  G11C2029/5002 ,  G11C2029/5006

Abstract: The present disclosure relates to a structure which includes a twin-cell memory which is configured to program a plurality of write operations, a current sense amplifier which is connected to the twin-cell memory and is configured to sense a current differential and latch a differential voltage based on the current differential, and at least one current source which is connected to the current sense amplifier and is configured to add an offset current to the current sense amplifier to create the differential voltage.

公开(公告)号：US20180075921A1

公开(公告)日：2018-03-15

申请号：US15790543

申请日：2017-10-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： John A. FIFIELD ,  Eric D. HUNT-SCHROEDER

IPC: G11C17/18

CPC classification number: G11C17/18 ,  G11C5/147 ,  G11C8/08

Abstract: The present disclosure relates to a method of generating a high differential read current through a non-volatile memory, including receiving a voltage read input from a word line voltage generator, outputting a first current to a bit line true (BLT), outputting a second current to a bit line complement (BLC), and generating the high differential read current through a difference between the first current and the second current.

公开(公告)号：US20170270999A1

公开(公告)日：2017-09-21

申请号：US15076139

申请日：2016-03-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Eric D. HUNT-SCHROEDER ,  John A. FIFIELD ,  Mark D. JACUNSKI

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/145 ,  G11C7/12 ,  G11C11/417

Abstract: Approaches for a write assist circuit are provided. The write assist circuit includes a boost capacitor with a first node coupled to a bitline through control logic and a second node connected to a field effect transistor (FET) diode stack, a plurality of boot enabled transistors which each contain a gate connected to a boost control signal, and a controlled current source coupled between a ground signal and the second node of the boost capacitor. In the write assist circuit, the boost capacitor has a discharge path which is controlled to provide a boost voltage which is invariant to a level of a power supply signal.

公开(公告)号：US20190108895A1

公开(公告)日：2019-04-11

申请号：US15730107

申请日：2017-10-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： John A. FIFIELD

IPC: G11C29/50

Abstract: The present disclosure relates to a structure which includes a current-mirror control node which is configured to adjust a current margin and provide the adjusted current margin to at least one one-time programmable memory (OTPM) cell.

公开(公告)号：US20190108894A1

公开(公告)日：2019-04-11

申请号：US15730078

申请日：2017-10-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： John A. FIFIELD ,  Eric D. HUNT-SCHROEDER ,  Darren L. ANAND

IPC: G11C29/50 ,  H01L27/11517 ,  G11C16/04

CPC classification number: G11C29/50004 ,  G11C16/0408 ,  G11C16/0441 ,  G11C16/10 ,  G11C2029/5004 ,  H01L27/11517

Abstract: The present disclosure relates to a structure which includes a twin-cell memory which includes a first device and a second device and which is configured to store data which corresponds to a threshold voltage difference between the first device controlled by a first wordline and the second device controlled by a second wordline.

公开(公告)号：US20170365302A1

公开(公告)日：2017-12-21

申请号：US15695457

申请日：2017-09-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Darren L. ANAND ,  John A. FIFIELD ,  Eric D. HUNT-SCHROEDER ,  Mark D. JACUNSKI

IPC: G11C7/06 ,  G11C17/18

Abstract: A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.