公开(公告)号：US20170270999A1

公开(公告)日：2017-09-21

申请号：US15076139

申请日：2016-03-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Eric D. HUNT-SCHROEDER ,  John A. FIFIELD ,  Mark D. JACUNSKI

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/145 ,  G11C7/12 ,  G11C11/417

Abstract: Approaches for a write assist circuit are provided. The write assist circuit includes a boost capacitor with a first node coupled to a bitline through control logic and a second node connected to a field effect transistor (FET) diode stack, a plurality of boot enabled transistors which each contain a gate connected to a boost control signal, and a controlled current source coupled between a ground signal and the second node of the boost capacitor. In the write assist circuit, the boost capacitor has a discharge path which is controlled to provide a boost voltage which is invariant to a level of a power supply signal.

公开(公告)号：US20170365302A1

公开(公告)日：2017-12-21

申请号：US15695457

申请日：2017-09-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Darren L. ANAND ,  John A. FIFIELD ,  Eric D. HUNT-SCHROEDER ,  Mark D. JACUNSKI

IPC: G11C7/06 ,  G11C17/18

Abstract: A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.