公开(公告)号：US09329890B2

公开(公告)日：2016-05-03

申请号：US14037925

申请日：2013-09-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Fadi Y. Busaba ,  Harold W. Cain, III ,  Michael K. Gschwind ,  Maged M. Michael ,  Valentina Salapura ,  Eric M. Schwarz ,  Chung-Lung K. Shum

IPC: G06F13/12 ,  G06F9/46 ,  G06F12/08 ,  G06F3/038 ,  G06F1/16 ,  G06F13/38

CPC classification number: G06F9/467 ,  G06F1/1632 ,  G06F3/038 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/385 ,  G06F2212/1016 ,  G06F2212/502

Abstract: Cache lines in a multi-processor computing environment are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. A high-coherence-miss cache line may be placed in sub-line coherency mode. A cache line may be associated with a counter in a coherence miss detection table that is incremented whenever an access of the cache line results in a coherence request. The cache line may be a high-coherence-miss cache line when the counter satisfies a high-coherence-miss criterion, such as reaching a threshold value. The cache line may be returned to full-line coherency mode when a reset criterion is satisfied.

Abstract translation: 多处理器计算环境中的高速缓存行可通过一致性模式进行配置。 全线一致性模式下的高速缓存行以全行粒度运行或管理。 子行一致性模式下的高速缓存行作为完整高速缓存行的子高速缓存行部分进行操作或管理。 高相干缺失高速缓存线可以被置于子线一致性模式中。 高速缓存行可以与相干未验证表中的计数器相关联，每当高速缓存行的访问导致一致性请求时，其将递增。 当计数器满足诸如达到阈值的高相干错误准则时，高速缓存行可以是高相干错失高速缓存行。 当满足复位标准时，高速缓存行可以返回到全线一致性模式。

公开(公告)号：US09298626B2

公开(公告)日：2016-03-29

申请号：US14037879

申请日：2013-09-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Fadi Y. Busaba ,  Harold W. Cain, III ,  Michael K. Gschwind ,  Maged M. Michael ,  Valentina Salapura ,  Eric M. Schwarz ,  Chung-Lung K. Shum

IPC: G06F13/12 ,  G06F12/08 ,  G06F9/30

CPC classification number: G06F12/0828 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/0831

Abstract: Cache lines in a computing environment with transactional memory are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. When a transaction accessing a cache line in full-line coherency mode results in a transactional abort, the cache line may be placed in sub-line coherency mode if the cache line is a high-conflict cache line. The cache line may be associated with a counter in a conflict address detection table that is incremented whenever a transaction conflict is detected for the cache line. The cache line may be a high-conflict cache line when the counter satisfies a high-conflict criterion, such as reaching a threshold value. The cache line may be returned to full-line coherency mode when a reset criterion is satisfied.

Abstract translation: 具有事务性存储器的计算环境中的高速缓存行可使用一致性模式进行配置。 全线一致性模式下的高速缓存行以全行粒度运行或管理。 子行一致性模式下的高速缓存行作为完整高速缓存行的子高速缓存行部分进行操作或管理。 当以全线一致性模式访问高速缓存行的事务导致事务中止时，如果高速缓存行是高冲突高速缓存行，则高速缓存行可以被置于子行一致性模式。 高速缓存行可以与冲突地址检测表中的计数器相关联，每当检测到高速缓存行的事务冲突时，它将递增。 当计数器满足诸如达到阈值的高冲突标准时，高速缓存行可以是高冲突高速缓存行。 当满足复位标准时，高速缓存行可以返回到全线一致性模式。

公开(公告)号：US09298623B2

公开(公告)日：2016-03-29

申请号：US14037901

申请日：2013-09-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Fadi Y. Busaba ,  Harold W. Cain, III ,  Michael K. Gschwind ,  Maged M. Michael ,  Valentina Salapura ,  Eric M. Schwarz ,  Chung-Lung K. Shum

IPC: G06F13/12 ,  G06F12/08 ,  G06F9/46

CPC classification number: G06F12/0815 ,  G06F9/467 ,  G06F9/528 ,  G06F12/0831 ,  G06F2212/1016 ,  G06F2212/502

Abstract: Cache lines in a computing environment with transactional memory are configurable with a coherency mode and are associated with a high-conflict indicator. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. A cache line is placed in sub-line coherency mode based on examining the high-conflict indicator. A transaction accessing a memory address in a cache line in sub-line coherency mode marks only the sub-cache line portion associated with the memory address as transactionally accessed. The high-conflict indicator may be included in a set of descriptive bits associated with the cache line. A copy of the high-conflict indicator for a cache line in a first cache may be updated with the high-conflict indicator for the cache line in a second cache.

Abstract translation: 具有事务性存储器的计算环境中的高速缓存行可使用一致性模式进行配置，并与高冲突指示器相关联。 全线一致性模式下的高速缓存行以全行粒度运行或管理。 子行一致性模式下的高速缓存行作为完整高速缓存行的子高速缓存行部分进行操作或管理。 基于检查高冲突指标，缓存行被置于子行一致性模式中。 以子行一致性模式访问高速缓存行中的存储器地址的事务仅将与存储器地址相关联的子高速缓存行部分标记为事务访问。 高冲突指示符可以被包括在与高速缓存行相关联的一组描述性位中。 可以用第二高速缓存中的高速缓存行的高冲突指示符来更新第一高速缓存中的高速缓存行的高冲突指示符的副本。