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公开(公告)号:US09773811B2
公开(公告)日:2017-09-26
申请号:US15049572
申请日:2016-02-22
Applicant: GLOBALFOUNDRIES Inc.
Inventor: Ingolf Lorenz , Stefan Block , Ulrich Hensel , Jürgen Faul , Michael Zier , Haritez Narisetty
CPC classification number: H01L27/1207 , H01L27/0255 , H01L27/1203 , H01L29/0649 , H01L29/66121 , H01L29/66568 , H01L29/861
Abstract: It is provided a semiconductor device comprising a power line, a Silicon-on-Insulator, SOI, substrate comprising a semiconductor layer and a semiconductor bulk substrate comprising a first doped region, a first transistor device formed in and above the SOI substrate and comprising a first gate dielectric formed over the semiconductor layer and a first gate electrode formed over the gate dielectric, a first diode electrically connected to the first gate electrode and a second diode electrically connected to the first diode and the power line; and wherein the first and second diodes are partially formed in the first doped region.
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公开(公告)号:US20170243894A1
公开(公告)日:2017-08-24
申请号:US15049572
申请日:2016-02-22
Applicant: GLOBALFOUNDRIES Inc.
Inventor: Ingolf Lorenz , Stefan Block , Ulrich Hensel , Jürgen Faul , Michael Zier , Haritez Narisetty
CPC classification number: H01L27/1207 , H01L27/0255 , H01L27/1203 , H01L29/0649 , H01L29/66121 , H01L29/66568 , H01L29/861
Abstract: It is provided a semiconductor device comprising a power line, a Silicon-on-Insulator, SOI, substrate comprising a semiconductor layer and a semiconductor bulk substrate comprising a first doped region, a first transistor device formed in and above the SOI substrate and comprising a first gate dielectric formed over the semiconductor layer and a first gate electrode formed over the gate dielectric, a first diode electrically connected to the first gate electrode and a second diode electrically connected to the first diode and the power line; and wherein the first and second diodes are partially formed in the first doped region.
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