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    Laser trimming of resistors
    2.
    发明授权
    Laser trimming of resistors 有权
    激光微调电阻

    公开(公告)号：US07297896B2

    公开(公告)日：2007-11-20

    申请号：US11254253

    申请日：2005-10-19

    Applicant: Nicholas Biunno ,  Atul Patel ,  Ken Ogle ,  George Dudnikov

    Inventor： Nicholas Biunno ,  Atul Patel ,  Ken Ogle ,  George Dudnikov

    IPC: B23K26/38 ,  G06F19/00

    CPC classification number: H01C17/242 ,  H05K1/167

    Abstract: Improved systems and methods for laser trimming resistors are provided. An exemplary embodiment measures a resistance value for each resistor and sorts the resistors into one or more bins based on the measured resistance values and target resistance values associated with each resistor. A laser trim file may then be assigned to each bin based on a predictive trim formulation, where each laser trim file defines a set of configuration parameters for a laser drill to conform each resistor with their respective target value. The laser drill uses the laser trim files to trim the resistors within each bin in accordance with the laser trim file assigned to that bin.

    Abstract translation: 提供了改进的激光微调电阻的系统和方法。 一个示例性实施例测量每个电阻器的电阻值，并且基于测量的电阻值和与每个电阻器相关联的目标电阻值，将电阻器分类成一个或多个箱体。 然后可以基于预测装饰公式将激光修剪文件分配给每个仓，其中每个激光修剪文件定义一组激光钻孔的配置参数，以使每个电阻器具有其各自的目标值。 激光钻孔机使用激光修剪文件根据分配给该纸盒的激光修剪文件来修整每个纸槽内的电阻器。

    EMBEDDED CAPACITIVE STACK
    3.
    发明申请
    EMBEDDED CAPACITIVE STACK 有权
    嵌入式电容堆叠

    公开(公告)号：US20080216298A1

    公开(公告)日：2008-09-11

    申请号：US12045656

    申请日：2008-03-10

    Applicant: George Dudnikov

    Inventor： George Dudnikov

    IPC: H01G4/30 ,  H05K3/20

    CPC classification number: H05K1/162 ,  H01G4/06 ,  H01G4/30 ,  H01G4/306 ,  H05K1/0216 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/18 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/0191 ,  H05K2201/0209 ,  H05K2201/0257 ,  H05K2201/0355 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09518 ,  H05K2201/09663 ,  H05K2203/162 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49036 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155

    Abstract: A novel method for manufacturing embedded a capacitive stack and a novel capacitive stack apparatus are provided having a capacitive core that serves as a structural substrate on which alternating thin conductive foils and nanopowder-loaded dielectric layers may be added and tested for reliability. This layering and testing allows early fault detection of the thin dielectric layers of the capacitive stack. The capacitive stack may be configured to supply multiple isolated capacitive elements that provide segregated, device-specific decoupling capacitance to one or more electrical components. The capacitive stack may serve as a core substrate on which a plurality of additional signaling layers of a multilayer circuit board may be coupled.

    Abstract translation: 提供了一种用于制造嵌入式电容堆叠的新方法和一种新颖的电容堆叠装置，其具有用作结构衬底的电容性芯，其上可以添加交替的薄导电箔和纳米粉末负载的电介质层并进行可靠性测试。 这种分层和测试允许电容堆叠的薄介电层的早期故障检测。 电容堆叠可以被配置为提供多个隔离的电容元件，其向一个或多个电气元件提供隔离的，器件特定的去耦电容。 电容堆叠可以用作核心衬底，多层电路板的多个附加信号层可以耦合在其上。

    Laser trimming of resistors
    5.
    发明申请
    Laser trimming of resistors 有权
    激光微调电阻

    公开(公告)号：US20060213882A1

    公开(公告)日：2006-09-28

    申请号：US11254253

    申请日：2005-10-19

    Applicant: Nicholas Biunno ,  Atul Patel ,  Ken Ogle ,  George Dudnikov

    Inventor： Nicholas Biunno ,  Atul Patel ,  Ken Ogle ,  George Dudnikov

    IPC: B23K26/36

    CPC classification number: H01C17/242 ,  H05K1/167

    Abstract: Improved systems and methods for laser trimming resistors are provided. An exemplary embodiment measures a resistance value for each resistor and sorts the resistors into one or more bins based on the measured resistance values and target resistance values associated with each resistor. A laser trim file may then be assigned to each bin based on a predictive trim formulation, where each laser trim file defines a set of configuration parameters for a laser drill to conform each resistor with their respective target value. The laser drill uses the laser trim files to trim the resistors within each bin in accordance with the laser trim file assigned to that bin.

    Abstract translation: 提供了改进的激光微调电阻的系统和方法。 一个示例性实施例测量每个电阻器的电阻值，并且基于测量的电阻值和与每个电阻器相关联的目标电阻值，将电阻器分类成一个或多个箱体。 然后可以基于预测装饰公式将激光修剪文件分配给每个仓，其中每个激光修剪文件定义一组激光钻孔的配置参数，以使每个电阻器具有其各自的目标值。 激光钻孔机使用激光修剪文件根据分配给该纸盒的激光修剪文件来修整每个纸槽内的电阻。

    Laser trimming of resistors
    8.
    发明申请
    Laser trimming of resistors 有权
    激光微调电阻

    公开(公告)号：US20050168318A1

    公开(公告)日：2005-08-04

    申请号：US11094003

    申请日：2005-03-29

    Applicant: Nicholas Biunno ,  Atul Patel ,  Ken Ogle ,  George Dudnikov

    Inventor： Nicholas Biunno ,  Atul Patel ,  Ken Ogle ,  George Dudnikov

    IPC: H01C17/242 ,  H05K1/11 ,  H05K1/16 ,  H05K3/02 ,  H01C10/00

    CPC classification number: H05K1/167 ,  B23K26/351 ,  H01C17/242 ,  H05K1/116 ,  H05K3/027 ,  H05K2203/171

    Abstract: Improved systems and methods for laser trimming resistors printed on a substrate layer are provided. An exemplary embodiment measures a resistance value for each annular resistor and sorts the annular resistors into one or more bins based on the measured resistance values and target resistance values associated with each resistor. A laser trim file may then be assigned to each bin based on a predictive trim formulation, where each laser trim file defines a set of configuration parameters for a laser drill to conform each resistor with their respective target value. The laser drill uses the laser trim files to trim the resistors within each bin in accordance with the laser trim file assigned to that bin.

    Abstract translation: 提供了改进的印刷在基底层上的激光微调电阻的系统和方法。 示例性实施例测量每个环形电阻器的电阻值，并且基于所测量的电阻值和与每个电阻器相关联的目标电阻值，将环形电阻器分类成一个或多个箱体。 然后可以基于预测装饰公式将激光修剪文件分配给每个仓，其中每个激光修剪文件定义一组激光钻孔的配置参数，以使每个电阻器具有其各自的目标值。 激光钻孔机使用激光修剪文件根据分配给该纸盒的激光修剪文件来修整每个纸槽内的电阻器。

    Embedded capacitive stack
    10.
    发明授权
    Embedded capacitive stack 有权
    嵌入式电容堆栈

    公开(公告)号：US08713769B2

    公开(公告)日：2014-05-06

    申请号：US12045656

    申请日：2008-03-10

    Applicant: George Dudnikov

    Inventor： George Dudnikov

    IPC: H01G7/00

    CPC classification number: H05K1/162 ,  H01G4/06 ,  H01G4/30 ,  H01G4/306 ,  H05K1/0216 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/18 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/0191 ,  H05K2201/0209 ,  H05K2201/0257 ,  H05K2201/0355 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09518 ,  H05K2201/09663 ,  H05K2203/162 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49036 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155

    Abstract: A novel method for manufacturing embedded a capacitive stack and a novel capacitive stack apparatus are provided having a capacitive core that serves as a structural substrate on which alternating thin conductive foils and nanopowder-loaded dielectric layers may be added and tested for reliability. This layering and testing allows early fault detection of the thin dielectric layers of the capacitive stack. The capacitive stack may be configured to supply multiple isolated capacitive elements that provide segregated, device-specific decoupling capacitance to one or more electrical components. The capacitive stack may serve as a core substrate on which a plurality of additional signaling layers of a multilayer circuit board may be coupled.

    Abstract translation: 提供了一种用于制造嵌入式电容堆叠的新方法和一种新颖的电容堆叠装置，其具有用作结构衬底的电容性芯，其上可以添加交替的薄导电箔和纳米粉末负载的电介质层并进行可靠性测试。 这种分层和测试允许电容堆叠的薄介电层的早期故障检测。 电容堆叠可以被配置为提供多个隔离的电容元件，其向一个或多个电气元件提供隔离的，器件特定的去耦电容。 电容堆叠可以用作核心衬底，多层电路板的多个附加信号层可以耦合在其上。

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