公开(公告)号：US20240019490A1

公开(公告)日：2024-01-18

申请号：US17812937

申请日：2022-07-15

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Naysen J. Robertson ,  Christopher M. Wesneski ,  Samuel Gonzalez

IPC: G01R31/317 ,  G01R31/3185

CPC classification number: G01R31/31727 ,  G01R31/3185

Abstract: In some examples, a computing device includes a first reset domain including a test controller and a configurable test logic. The computing device includes a second reset domain including a subsystem to be measured by the configurable test logic. The first reset domain is to enter a reset mode, and after exiting the reset mode, receive configuration information that configures the configurable test logic. The test controller of the first reset domain is to maintain the second reset domain in a reset mode after the first reset domain has exited the reset mode of the first reset domain, and responsive to the received configuration information for configuring the configurable test logic, provide a reset release indication to the second reset domain to allow the second reset domain to exit the reset mode of the second reset domain.

公开(公告)号：US20240168784A1

公开(公告)日：2024-05-23

申请号：US18058127

申请日：2022-11-22

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Naysen J. Robertson ,  Samuel Gonzalez ,  David A. Young ,  Theodore F. Emerson ,  Nathaniel W. Jansen

IPC: G06F9/455

CPC classification number: G06F9/45529

Abstract: A process includes emulating, by a programmable logic device, a hardware component to provide an emulated hardware component. The emulated hardware component is capable of exercising the predetermined functionality. The process includes testing the emulated hardware component. The process includes determining, by the programmable logic device, whether the emulated hardware component exercised the predetermined functionality during the test. The determination includes, responsive to the testing, detecting, by a state sequence detector of the programmable logic device, whether the emulated hardware component sequenced through a plurality of states associated with the predetermined functionality. The process includes, responsive to the detection of whether the emulated hardware component sequenced through the plurality of states, generating, by the programmable logic device, an indicator representing a coverage of the predetermined functionality by the testing.

公开(公告)号：US11899066B2

公开(公告)日：2024-02-13

申请号：US17812937

申请日：2022-07-15

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Naysen J. Robertson ,  Christopher M. Wesneski ,  Samuel Gonzalez

IPC: G01R31/3185 ,  G06F30/34 ,  G01R31/317

CPC classification number: G01R31/3185 ,  G06F30/34 ,  G01R31/31727

Abstract: In some examples, a computing device includes a first reset domain including a test controller and a configurable test logic. The computing device includes a second reset domain including a subsystem to be measured by the configurable test logic. The first reset domain is to enter a reset mode, and after exiting the reset mode, receive configuration information that configures the configurable test logic. The test controller of the first reset domain is to maintain the second reset domain in a reset mode after the first reset domain has exited the reset mode of the first reset domain, and responsive to the received configuration information for configuring the configurable test logic, provide a reset release indication to the second reset domain to allow the second reset domain to exit the reset mode of the second reset domain.