公开(公告)号：US10211200B2

公开(公告)日：2019-02-19

申请号：US15883591

申请日：2018-01-30

Applicant: INDIAN INSTITUTE OF SCIENCE

Inventor： Mayank Shrivastava ,  Milova Paul ,  Christian Russ ,  Harald Gossner

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/78

Abstract: The present disclosure relates to a Silicon Controlled Rectifier (SCR) in non-planar technology to provide a robust ESD protection in System on Chip employing non-planar technologies. The disclosed SCR incorporates wire or fin shaped nanostructures extending from p-type tap to cathode, from the cathode to anode, and from the anode to n-type tap to provide parallel trigger paths to prevent problem of current crowding at the base emitter junction that limits efficient turn-on in conventional SCRs. The proposed structure helps in offering lower trigger and holding voltage, and therefore very high failure currents. The disclosed SCR has sub-3V trigger and holding voltage to provide an efficient and robust ESD protection in SOCs. The proposed device also offers three times better ESD robustness per unit area. Further the proposed SCR has no added capacitive loading and is compatible with standard process flow and design rules.

公开(公告)号：US10483258B2

公开(公告)日：2019-11-19

申请号：US15899117

申请日：2018-02-19

Applicant: Indian Institute of Science

Inventor： Mayank Shrivastava ,  Milova Paul ,  Harald Gossner

IPC: H01L27/02 ,  H01L27/12 ,  H01L29/78 ,  H01L29/74 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/06

Abstract: The present disclosure relates to non-planar ESD protection devices. The present disclosure provides a device structure and method of fabricating the structure that is essentially immune to latch-up and possess high ESD robustness and reliability. In an aspect, the present disclosure provides a mixed silicidation and selective epitaxy (epi) FinFET processes for latch-up immunity together with ESD robustness, thereby allowing achievement of ESD efficient parasitic structures together with latch-up immune and reliable functional devices. The present disclosure provides a dual silicidation scheme where ESD protection element(s) have fins that are partially silicided, and functional devices have fins that are fully silicided. The present disclosure also provides a hybrid contact and junction profile scheme where ESD protection element(s) have fins that are partially silicided with or without deep junctions depending on their application, and functional devices have fins that are fully silicided with the silicide edge crossing the junction. On the other hand, a dual Epi scheme is implemented such that ESD protection elements have fins with Epi contact, and functional devices have fins that are fully silicided without Epi (raised S/D) contact.

公开(公告)号：US20180248025A1

公开(公告)日：2018-08-30

申请号：US15899102

申请日：2018-02-19

Applicant: Indian Institute of Science

Inventor： Mayank Shrivastava ,  Milova Paul ,  Harald Gossner

IPC: H01L29/74 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

Abstract: SCRs are a must for ESD protection in low voltage—high speed I/O as well as ESD protection of RF pads due to least parasitic loading and smallest foot print offered by SCRs. However, conventionally designed SCRs in FinFET and Nanowire technology suffer from very high turn-on and holding voltage. This issue becomes more severe in sub-14 nm non-planar technologies and cannot be handled by conventional approaches like diode- or transient-turn-on techniques. Proposed invention discloses SCR concept for FinFET and Nanowire technology with diffused junction profiles with sub-3V trigger and holding voltage for efficient and robust ESD protection. Besides low trigger and holding voltage, the proposed device offers a 3 times better ESD robustness per unit area.

公开(公告)号：US20180247929A1

公开(公告)日：2018-08-30

申请号：US15899117

申请日：2018-02-19

Applicant: Indian Institute of Science

Inventor： Mayank Shrivastava ,  Milova Paul ,  Harald Gossner

IPC: H01L27/02 ,  H01L27/088 ,  H01L27/12 ,  H01L29/78 ,  H01L29/74 ,  H01L21/8234

Abstract: The present disclosure relates to non-planar ESD protection devices. The present disclosure provides a device structure and method of fabricating the structure that is essentially immune to latch-up and possess high ESD robustness and reliability. In an aspect, the present disclosure provides a mixed silicidation and selective epitaxy (epi) FinFET processes for latch-up immunity together with ESD robustness, thereby allowing achievement of ESD efficient parasitic structures together with latch-up immune and reliable functional devices. The present disclosure provides a dual silicidation scheme where ESD protection element(s) have fins that are partially silicided, and functional devices have fins that are fully silicided. The present disclosure also provides a hybrid contact and junction profile scheme where ESD protection element(s) have fins that are partially silicided with or without deep junctions depending on their application, and functional devices have fins that are fully silicided with the silicide edge crossing the junction. On the other hand, a dual Epi scheme is implemented such that ESD protection elements have fins with Epi contact, and functional devices have fins that are fully silicided without Epi (raised S/D) contact.

公开(公告)号：US10535762B2

公开(公告)日：2020-01-14

申请号：US15899102

申请日：2018-02-19

Applicant: Indian Institute of Science

Inventor： Mayank Shrivastava ,  Milova Paul ,  Harald Gossner

IPC: H01L29/74 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/45 ,  H01L29/78 ,  H01L21/285

Abstract: SCRs are a must for ESD protection in low voltage—high speed I/O as well as ESD protection of RF pads due to least parasitic loading and smallest foot print offered by SCRs. However, conventionally designed SCRs in FinFET and Nanowire technology suffer from very high turn-on and holding voltage. This issue becomes more severe in sub-14 nm non-planar technologies and cannot be handled by conventional approaches like diode- or transient-turn-on techniques. Proposed invention discloses SCR concept for FinFET and Nanowire technology with diffused junction profiles with sub-3V trigger and holding voltage for efficient and robust ESD protection. Besides low trigger and holding voltage, the proposed device offers a 3 times better ESD robustness per unit area.

公开(公告)号：US10319662B2

公开(公告)日：2019-06-11

申请号：US15883749

申请日：2018-01-30

Applicant: INDIAN INSTITUTE OF SCIENCE

Inventor： Mayank Shrivastava ,  Milova Paul ,  Christian Russ ,  Harald Gossner

IPC: H01L23/367 ,  H01L27/088 ,  H01L29/423 ,  H01L29/74 ,  H01L29/861 ,  H01L29/06 ,  H01L27/02 ,  H01L29/735

Abstract: The present disclosure relates to a thermal management solution for ESD protection devices in advanced Fin- and/or Nanowire-based technology nodes, by employing localized nano heat sinks, which enable heat transport from local hot spots to surface of chip, which allows significant reduction in peak temperature for a given ESD current. In an aspect, the proposed semiconductor device can include at least one fin having a source and a drain disposed over a p-well or a n-well in a substrate; an electrically floating dummy metal gate disposed close to drain or hot spot over at least a portion of the at least one fin, and an electrical metal gate is disposed close to the source; and a nano-heat sink operatively coupled with the dummy metal gate and terminating at the surface of chip in which the semiconductor device is configured so as to enable transfer of heat received from the at least one fin through the dummy metal gate to the surface of the chip.