公开(公告)号：US20220148951A1

公开(公告)日：2022-05-12

申请号：US17544221

申请日：2021-12-07

Applicant: Infineon Technologies AG

Inventor： Ngoc-Hoa Huynh ,  Franz-Xaver Muehlbauer ,  Claus Waechter ,  Veronika Theyerl ,  Dominic Maier ,  Thomas Kilger ,  Saverio Trotta ,  Ashutosh Baheti ,  Georg Meyer-Berg ,  Maciej Wojnowski

IPC: H01L23/498 ,  H01L23/367 ,  H01L23/538 ,  H01Q9/28 ,  H01Q1/22 ,  H01Q9/04 ,  H01Q21/06 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor device includes a semiconductor chip and a redistribution layer on a first side of the semiconductor chip. The redistribution layer is electrically coupled to the semiconductor chip. The semiconductor device includes a dielectric layer and an antenna on the dielectric layer. The dielectric layer is between the antenna and the semiconductor chip.

公开(公告)号：US20210172862A1

公开(公告)日：2021-06-10

申请号：US16951365

申请日：2020-11-18

Applicant: Infineon Technologies AG

Inventor： Siyuan Qi ,  Joachim Eder ,  Christoph Glacer ,  Dominic Maier ,  Mark Pavier

IPC: G01N21/17 ,  B81B3/00 ,  B81B7/00 ,  B81C1/00

Abstract: The present disclosure concerns an emitter package for a photoacoustic sensor, the emitter package comprising a MEMS infrared radiation source for emitting pulsed infrared radiation in a first wavelength range. The MEMS infrared radiation source may be arranged on a substrate. The emitter package may further comprise a rigid wall structure being arranged on the substrate and laterally surrounding a periphery of the MEMS infrared radiation source. The emitter package may further comprise a lid structure being attached to the rigid wall structure, the lid structure comprising a filter structure for filtering the infrared radiation emitted from the MEMS infrared radiation source and for providing a filtered infrared radiation in a reduced second wavelength range.

公开(公告)号：US10600690B2

公开(公告)日：2020-03-24

申请号：US16102174

申请日：2018-08-13

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Claus von Waechter ,  Michael Bauer ,  Holger Doepke ,  Dominic Maier ,  Daniel Porwol ,  Tobias Schmidt

IPC: B32B37/26 ,  B32B38/10 ,  H01L21/78 ,  H01L21/683 ,  H01L21/56 ,  H01L23/00 ,  B32B7/027 ,  H05K3/00 ,  B32B7/06

Abstract: A method for handling a product substrate includes bonding a carrier to the product substrate by: applying a layer of a temporary adhesive having a first coefficient of thermal expansion onto a surface of the carrier; and bonding the carrier to the product substrate using the applied temporary adhesive. A surface of the temporary adhesive is in direct contact to a surface of the product substrate. The temporary adhesive includes or is adjacent a filler material having a second coefficient of thermal expansion which is smaller than the first coefficient of thermal expansion, so that stress occurs inside the temporary adhesive layer or at an interface to the product substrate or the carrier during cooling down of the temporary adhesive layer.

公开(公告)号：US20160311679A1

公开(公告)日：2016-10-27

申请号：US15138313

申请日：2016-04-26

Applicant: Infineon Technologies AG

Inventor： Dominic Maier ,  Alfons Dehe ,  Thomas Kilger ,  Markus Menath ,  Franz Xaver Muehlbauer ,  Daniel Porwol ,  Juergen Wagner

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00896 ,  B81C1/00269 ,  B81C1/00801 ,  B81C2201/0194 ,  B81C2201/053

Abstract: A method of producing a chip package is described. A plurality of chips is provided on a first wafer. Each chip has a cavity which opens to a first main face of the chip. The cavities are filled or covered temporarily. The chips are then singulated. The singulated chips are embedded in an encapsulation material, and then the cavities are re-exposed.

Abstract translation: 对芯片封装的制造方法进行说明。 多个芯片设置在第一晶片上。 每个芯片具有通向芯片的第一主面的空腔。 空腔被暂时填充或覆盖。 然后将芯片分开。 单片化芯片嵌入封装材料中，然后将空腔重新曝光。

公开(公告)号：US09147585B2

公开(公告)日：2015-09-29

申请号：US14535591

申请日：2014-11-07

Applicant: Infineon Technologies AG

Inventor： Thomas Kilger ,  Ulrich Wachter ,  Dominic Maier ,  Gottfried Beer

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/82 ,  H01L21/56 ,  H01L23/538 ,  H01L27/04 ,  H01L49/02 ,  H01L23/00 ,  H01L21/78 ,  H01L25/00 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L21/82 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L25/50 ,  H01L27/04 ,  H01L28/00 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/00

Abstract: A number of semiconductor chips each include a first main face and a second main face opposite to the first main face. A first encapsulation layer is applied over the second main faces of the semiconductor chips. An electrical wiring layer is applied over the first main faces of the first semiconductor chips. A second encapsulation layer is applied over the electrical wiring layer. The thickness of the first encapsulation layer and the thicknesses of the first semiconductor chips is reduced. The structure can be singulated to obtain a plurality of semiconductor devices.

Abstract translation: 多个半导体芯片各自包括与第一主面相对的第一主面和第二主面。 在半导体芯片的第二主面上施加第一封装层。 在第一半导体芯片的第一主面上施加电布线层。 将第二封装层施加在电布线层上。 第一封装层的厚度和第一半导体芯片的厚度减小。 可以将该结构单个化以获得多个半导体器件。

公开(公告)号：US09099454B2

公开(公告)日：2015-08-04

申请号：US13964153

申请日：2013-08-12

Applicant: Infineon Technologies AG

Inventor： Ulrich Wachter ,  Veronika Huber ,  Thomas Kilger ,  Ralf Otremba ,  Bernd Stadler ,  Dominic Maier ,  Klaus Schiess ,  Andreas Schlögl ,  Uwe Wahl

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/36 ,  H01L21/56

CPC classification number: H01L23/49575 ,  H01L21/561 ,  H01L21/568 ,  H01L23/36 ,  H01L23/49562 ,  H01L24/24 ,  H01L24/25 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/96 ,  H01L27/14618 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/73273 ,  H01L2224/73277 ,  H01L2224/85 ,  H01L2224/96 ,  H01L2924/12043 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2924/00014

Abstract: A semiconductor package is manufactured by providing a semiconductor die with a terminal at a first side of the die, providing a material coupled to the die at an opposing second side of the die and embedding the die in a molding compound so that the die is covered by the molding compound on all sides except the first side. The molding compound is thinned at a side of the molding compound adjacent the second side of the die, to expose the material at the second side of the die without exposing the second side of the die. An electrical connection is formed to the terminal at the first side of the die. In the case of a transistor die, the terminal can be a source terminal and the transistor die can be attached source-down to a metal block such as a die paddle of a lead frame.

Abstract translation: 通过在模具的第一侧提供具有端子的半导体模具来制造半导体封装，在模具的相对的第二侧提供耦合到模具的材料，并将模具嵌入模制化合物中，使得模具被覆盖 通过除第一面以外的所有侧面的模塑料。 模塑料在靠近模具的第二侧的模塑料的一侧变细，以在模具的第二面露出材料，而不暴露模具的第二面。 在模具的第一侧上的端子形成电连接。 在晶体管管芯的情况下，端子可以是源极端子，并且晶体管管芯可以源极地附接到诸如引线框架的管芯焊盘的金属块。

公开(公告)号：US20150041967A1

公开(公告)日：2015-02-12

申请号：US13964153

申请日：2013-08-12

Applicant: Infineon Technologies AG

Inventor： Ulrich Wachter ,  Veronika Huber ,  Thomas Kilger ,  Ralf Otremba ,  Bernd Stadler ,  Dominic Maier ,  Klaus Schiess ,  Andreas Schlögl ,  Uwe Wahl

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L21/561 ,  H01L21/568 ,  H01L23/36 ,  H01L23/49562 ,  H01L24/24 ,  H01L24/25 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/96 ,  H01L27/14618 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/73273 ,  H01L2224/73277 ,  H01L2224/85 ,  H01L2224/96 ,  H01L2924/12043 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2924/00014

Abstract: A semiconductor package is manufactured by providing a semiconductor die with a terminal at a first side of the die, providing a material coupled to the die at an opposing second side of the die and embedding the die in a molding compound so that the die is covered by the molding compound on all sides except the first side. The molding compound is thinned at a side of the molding compound adjacent the second side of the die, to expose the material at the second side of the die without exposing the second side of the die. An electrical connection is formed to the terminal at the first side of the die. In the case of a transistor die, the terminal can be a source terminal and the transistor die can be attached source-down to a metal block such as a die paddle of a lead frame.

Abstract translation: 通过在模具的第一侧提供具有端子的半导体模具来制造半导体封装，在模具的相对的第二侧提供耦合到模具的材料，并将模具嵌入模制化合物中，使得模具被覆盖 通过除第一面以外的所有侧面的模塑料。 模塑料在靠近模具的第二侧的模塑料的一侧变细，以在模具的第二面露出材料，而不暴露模具的第二面。 在模具的第一侧上的端子形成电连接。 在晶体管管芯的情况下，端子可以是源极端子，并且晶体管管芯可以源极地附接到诸如引线框架的管芯焊盘的金属块。

公开(公告)号：US20240182297A1

公开(公告)日：2024-06-06

申请号：US18519897

申请日：2023-11-27

Applicant: Infineon Technologies AG

Inventor： Hutomo Suryo Wasisto ,  Fabian Streb ,  Sebastian Anzinger ,  Marc Füldner ,  Dominic Maier

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00285 ,  B81B7/0029 ,  B81B2201/0257 ,  B81C2201/0132 ,  H04R1/023 ,  H04R2201/003 ,  H04R2201/029

Abstract: A method for manufacturing a micromechanical environmental barrier chip includes providing a substrate having a first surface and an opposite second surface, depositing a material layer having a different etch characteristic than the substrate onto the first surface, creating a microstructured micromechanical environmental barrier structure on top of the material layer by applying a microstructuring process, applying an anisotropic etching process comprising at least one etching step for anisotropically etching from the second surface towards the first surface to create at least a cavity underneath the micromechanical environmental barrier structure, the cavity extending between the second surface and the material layer, and removing the material layer underneath the micromechanical environmental barrier structure to expose the environmental barrier structure.

公开(公告)号：US11279120B2

公开(公告)日：2022-03-22

申请号：US16504811

申请日：2019-07-08

Applicant: Infineon Technologies AG

Inventor： Alfred Sigi ,  Dominic Maier ,  Daniel Porwol

IPC: B32B41/00 ,  B32B38/10 ,  B32B38/18

Abstract: A device for debonding a structure from a main surface region of a carrier includes a tape for laminating to the structure, a first holder and a second holder for spanning the tape and to keep a tension of the tape. The second holder can be movable into a lifted position vertically offset to the main surface region of the carrier. The device can also include a deflecting-element for providing a deflection-line between the first holder and the second holder for deflecting the tape in response to moving the second holder into the lifted position. The deflecting-element can be moveable parallel to the carrier for moving the deflection-line parallel to the carrier and for debonding the structure, laminated to the tape, from the carrier.

公开(公告)号：US20200051824A1

公开(公告)日：2020-02-13

申请号：US16654165

申请日：2019-10-16

Applicant: Infineon Technologies AG

Inventor： Stephan Pindl ,  Daniel Lugauer ,  Dominic Maier ,  Alfons Dehe

IPC: H01L21/306 ,  H01L23/31 ,  H01L21/762 ,  H01L21/02 ,  H01L21/302 ,  H01L21/20 ,  H01L21/18 ,  H01L33/00 ,  H01L23/057 ,  H01L23/053 ,  G01N27/12 ,  H01L23/29 ,  H01L23/00 ,  G01N27/02 ,  G01N33/00 ,  H01L21/56 ,  H01L23/538 ,  H05K1/18

Abstract: According to an embodiment, a sensor package includes an electrically insulating substrate including a cavity in the electrically insulating substrate, an ambient sensor, an integrated circuit die embedded in the electrically insulating substrate, and a plurality of conductive interconnect structures coupling the ambient sensor to the integrated circuit die. The ambient sensor is supported by the electrically insulating substrate and arranged adjacent the cavity.