公开(公告)号：US20230148014A1

公开(公告)日：2023-05-11

申请号：US17972910

申请日：2022-10-25

Applicant: Infineon Technologies AG

Inventor： Thomas Grille ,  Elmar Aschauer ,  Ulf Bartl ,  Christoph Kovatsch ,  Matic Krivec ,  Thomas Ostermann ,  Lukas Praster ,  Gerald Stocker

IPC: H02N2/18 ,  H02N2/00

CPC classification number: H02N2/186 ,  H02N2/22

Abstract: A MEMS component is described herein, which according to one exemplary embodiment includes: a semiconductor body; an insulation layer arranged on the semiconductor body; a boundary structure arranged on the insulation layer, the semiconductor body including an opening below the boundary structure; first and second structured electrodes arranged on the insulation layer; and a piezoelectric layer comprising a thermoplastic, and at least partially bounded by the boundary structure and arranged on the insulation layer and on the first and second electrodes.

公开(公告)号：US10586792B2

公开(公告)日：2020-03-10

申请号：US16236741

申请日：2018-12-31

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Markus Zundel ,  Peter Brandl ,  Kurt Matoy ,  Thomas Ostermann

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/06 ,  H01L29/786 ,  H01L29/40 ,  H01L49/02 ,  H01L29/739 ,  H01L29/808

Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.

公开(公告)号：US20180212085A1

公开(公告)日：2018-07-26

申请号：US15925904

申请日：2018-03-20

Applicant: Infineon Technologies AG

Inventor： Stefan CLARA ,  Thomas Grille ,  Ursula Hedenig ,  Peter Irsigler ,  Bernhard Jakoby ,  Ventsislav M. Lavchiev ,  Thomas Ostermann ,  Thomas Popp

IPC: H01L31/0352 ,  H01L31/18 ,  H01L33/06

CPC classification number: H01L31/035254 ,  H01L31/035209 ,  H01L31/035218 ,  H01L31/173 ,  H01L31/1812 ,  H01L31/1864 ,  H01L33/06 ,  H01L2933/0033

Abstract: A semiconductor device comprises a plurality of quantum structures comprising predominantly germanium. The plurality of quantum structures are formed on a first semiconductor layer structure. The quantum structures of the plurality of quantum structures have a lateral dimension of less than 15 nm and an area density of at least 8×1011 quantum structures per cm2. The plurality of quantum structures are configured to emit light with a light emission maximum at a wavelength of between 2 μm and 10 μm or to absorb light with a light absorption maximum at a wavelength of between 2 μm and 10 μm.

公开(公告)号：US20180114788A1

公开(公告)日：2018-04-26

申请号：US15792492

申请日：2017-10-24

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Markus Zundel ,  Peter Brandl ,  Kurt Matoy ,  Thomas Ostermann

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0292 ,  H01L27/0255 ,  H01L27/0288 ,  H01L27/0296 ,  H01L28/20 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/7395 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/78618 ,  H01L29/8083

Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.

公开(公告)号：US20210265497A1

公开(公告)日：2021-08-26

申请号：US17316067

申请日：2021-05-10

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Stefan Mieslinger ,  Thomas Ostermann ,  Andrew Christopher Graeme Wood

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/423

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes: a first active cell area comprising a first plurality of parallel gate trenches; a second active cell area comprising a second plurality of parallel gate trenches; and a metallization layer above the first and the second active cell areas. The metallization layer includes: a first part contacting a semiconductor mesa region between the plurality of parallel gate trenches in the first and the second active cell areas; and a second part surrounding the first part. The second part of the metallization layer contacts the first plurality of gate trenches along a first direction and the second plurality of gate trenches along a second direction different from the first direction.

公开(公告)号：US10672661B2

公开(公告)日：2020-06-02

申请号：US16176403

申请日：2018-10-31

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Stefan Mieslinger ,  Thomas Ostermann ,  Christian Westermeier ,  Jochen Hilsenbeck ,  Jens Peter Konrath ,  Boris Mayerhofer ,  Anatoly Sotnikov

IPC: H01L21/78 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40

Abstract: A semiconductor wafer having a main surface and a rear surface opposite from the main surface is provided. A die singulation preparation step is performed in kerf regions of the semiconductor wafer. The kerf regions enclose a plurality of die sites. The die singulation preparation step includes forming one or more preliminary kerf trenches between at least two immediately adjacent die sites. The method further includes forming active semiconductor devices in the die sites, and singulating the semiconductor wafer in the kerf regions thereby providing a plurality of discrete semiconductor dies from the die sites. The one or more preliminary kerf trenches are unfilled during the singulating, and the singulating includes removing semiconductor material from a surface of the semiconductor wafer that is between opposite facing sidewalls of the one or more preliminary kerf trenches.

公开(公告)号：US10217830B2

公开(公告)日：2019-02-26

申请号：US15373128

申请日：2016-12-08

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Thomas Ostermann ,  Michael Sorger

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78

Abstract: A semiconductor device includes a plurality of trenches extending into a semiconductor substrate. Each trench comprises a plurality of enlarged width regions distributed along the trench. At least one electrically conductive trench structure is located in each trench. The semiconductor device comprises an electrically insulating layer arranged between the semiconductor substrate and an electrode structure. The semiconductor device comprises a vertical electrically conductive structure extending through the electrically insulating layer. The vertical electrically conductive structure forms an electrically connection between the electrode structure and an electrically conductive trench structure located in a first trench of at a first enlarged width region. The electrically insulating layer is arranged between a second enlarged width region of the plurality of enlarged width regions of the first trench and an electrode structure above the second enlarged width region without any vertical electrical connections through the electrically insulating layer at the second enlarged width region.

公开(公告)号：US10199490B2

公开(公告)日：2019-02-05

申请号：US15915890

申请日：2018-03-08

Applicant: Infineon Technologies AG

Inventor： Adrian Finney ,  Radu Eugen Cazimirovici ,  Dietmar Kotz ,  Thomas Ostermann

IPC: H01L29/78 ,  H01L27/08 ,  H01L21/82 ,  H01L21/263 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/36 ,  H01L29/66

Abstract: A semiconductor device includes a guard structure located laterally between a first active area of a semiconductor substrate and a second active area of the semiconductor substrate. The guard structure includes a first doping region located at a front side surface of the semiconductor substrate, and a wiring structure electrically connecting the first doping region to a highly doped portion of a common doping region. The common doping region extends from a backside surface of the semiconductor substrate to at least a part of the front side surface of the semiconductor substrate in contact with the wiring structure of the guard structure. Corresponding methods for forming the semiconductor device are also described.

公开(公告)号：US20170373182A1

公开(公告)日：2017-12-28

申请号：US15627481

申请日：2017-06-20

Applicant: Infineon Technologies AG

Inventor： Adrian Finney ,  Dietmar Kotz ,  Radu Eugen Cazimirovici ,  Thomas Ostermann

IPC: H01L29/78 ,  H01L29/36 ,  H01L29/06 ,  H01L21/263 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7811 ,  H01L21/263 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/66712

Abstract: A semiconductor device includes a guard structure located laterally between first and second active areas of a semiconductor substrate. The guard structure includes a first doping region at a front side surface of the substrate and a wiring structure electrically connecting the first doping region to a highly doped portion of a common doping region. The common doping region extends from a backside surface of the substrate to at least a part of the front side surface in contact with the wiring structure. An edge termination doping region laterally surrounds the first and second active areas. The edge termination doping region and the first doping region have a first conductivity type, and the common doping region has a second conductivity type. A resistive connection between the edge termination doping region and the first doping region is present at least during reverse operating conditions of the semiconductor device.

公开(公告)号：US20150069394A1

公开(公告)日：2015-03-12

申请号：US14020117

申请日：2013-09-06

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Thomas Ostermann

IPC: H01L23/544 ,  H01L29/06 ,  H01L21/66

CPC classification number: H01L23/544 ,  H01L21/784 ,  H01L22/12 ,  H01L22/34 ,  H01L29/0657 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00 ,  H01L2224/03

Abstract: A device includes a semiconductor chip. An outline of a frontside of the semiconductor chip includes at least one of a polygonal line including two line segments joined together at an inner angle of greater than 90° and an arc-shaped line.

Abstract translation: 一种器件包括半导体芯片。 半导体芯片的前端的轮廓包括以大于90°的内角连接的两条线段和弧形线的折线。