公开(公告)号：US20190393350A1

公开(公告)日：2019-12-26

申请号：US16013329

申请日：2018-06-20

Applicant: INTEL CORPORATION

Inventor： Erica J. Thompson ,  Aditya Kasukurti ,  Jun Sung Kang ,  Kai Loon Cheong ,  Biswajeet Guha ,  William Hsu ,  Bruce Beattie

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

Abstract: A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.

公开(公告)号：US11715787B2

公开(公告)日：2023-08-01

申请号：US17514058

申请日：2021-10-29

Applicant: Intel Corporation

Inventor： Mark Armstrong ,  Biswajeet Guha ,  Jun Sung Kang ,  Bruce Beattie ,  Tahir Ghani

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/266 ,  H01L21/26506 ,  H01L21/30604 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7853

Abstract: A method comprising: forming a substrate; forming a first nanowire over the substrate; forming a second nanowire over the substrate; forming a gate over a portion of the first and second nanowires; implanting a dopant such that a region between the first and second nanowires under the gate does not receive the dopant while a region between the first and second nanowires away from the gate receives the dopant, wherein the dopant amorphize a material of the region between the first and second nanowires away from the gate; and isotopically etching of the region between the first and second nanowires away from the gate.

公开(公告)号：US11205715B2

公开(公告)日：2021-12-21

申请号：US16632856

申请日：2017-08-21

Applicant: Intel Corporation

Inventor： Mark Armstrong ,  Biswajeet Guha ,  Jun Sung Kang ,  Bruce Beattie ,  Tahir Ghani

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: A method comprising: forming a substrate; forming a first nanowire over the substrate; forming a second nanowire over the substrate; forming a gate over a portion of the first and second nanowires; implanting a dopant such that a region between the first and second nanowires under the gate does not receive the dopant while a region between the first and second nanowires away from the gate receives the dopant, wherein the dopant amorphize a material of the region between the first and second nanowires away from the gate; and isotopically etching of the region between the first and second nanowires away from the gate.

公开(公告)号：US11869973B2

公开(公告)日：2024-01-09

申请号：US16013329

申请日：2018-06-20

Applicant: INTEL CORPORATION

Inventor： Erica J. Thompson ,  Aditya Kasukurti ,  Jun Sung Kang ,  Kai Loon Cheong ,  Biswajeet Guha ,  William Hsu ,  Bruce Beattie

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/165 ,  H01L29/205 ,  H01L29/423

CPC classification number: H01L29/7853 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/7855 ,  H01L21/02238 ,  H01L21/02241 ,  H01L21/31111 ,  H01L21/31122 ,  H01L29/165 ,  H01L29/205 ,  H01L29/42392

Abstract: A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.

公开(公告)号：US11869891B2

公开(公告)日：2024-01-09

申请号：US16146808

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Jun Sung Kang ,  Kai Loon Cheong ,  Erica J. Thompson ,  Biswajeet Guha ,  William Hsu ,  Dax M. Crum ,  Tahir Ghani ,  Bruce Beattie

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/161 ,  H01L29/423

CPC classification number: H01L27/0924 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process are described. For example, an integrated circuit structure includes a fin or nanowire. A gate stack is over the fin or nanowire. The gate stack includes a gate dielectric and a gate electrode. A first dielectric spacer is along a first side of the gate stack, and a second dielectric spacer is along a second side of the gate stack. The first and second dielectric spacers are over at least a portion of the fin or nanowire. An insulating material is vertically between and in contact with the portion of the fin or nanowire and the first and second dielectric spacers. A first epitaxial source or drain structure is at the first side of the gate stack, and a second epitaxial source or drain structure is at the second side of the gate stack.

公开(公告)号：US11342411B2

公开(公告)日：2022-05-24

申请号：US16023511

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： William Hsu ,  Biswajeet Guha ,  Leonard Guler ,  Souvik Chakrabarty ,  Jun Sung Kang ,  Bruce Beattie ,  Tahir Ghani

IPC: H01L29/06 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  B82Y10/00

Abstract: A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.

公开(公告)号：US20240088296A1

公开(公告)日：2024-03-14

申请号：US18514974

申请日：2023-11-20

Applicant: Intel Corporation

Inventor： Erica J. THOMPSON ,  Aditya Kasukurti ,  Jun Sung Kang ,  Kai Loon Cheong ,  Biswajeet Guha ,  William Hsu ,  Bruce Beattie

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/7855 ,  H01L21/02238

Abstract: A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.

公开(公告)号：US20200152767A1

公开(公告)日：2020-05-14

申请号：US16632856

申请日：2017-08-21

Applicant: Intel Corporation

Inventor： Mark Armstrong ,  Biswajeet Guha ,  Jun Sung Kang ,  Bruce Beattie ,  Tahir Ghani

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/306 ,  H01L21/266 ,  H01L21/265

Abstract: A method comprising: forming a substrate; forming a first nanowire over the substrate; forming a second nanowire over the substrate; forming a gate over a portion of the first and second nanowires; implanting a dopant such that a region between the first and second nanowires under the gate does not receive the dopant while a region between the first and second nanowires away from the gate receives the dopant, wherein the dopant amorphize a material of the region between the first and second nanowires away from the gate; and isotopically etching of the region between the first and second nanowires away from the gate.

公开(公告)号：US20200006478A1

公开(公告)日：2020-01-02

申请号：US16023511

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： William Hsu ,  Biswajeet Guha ,  Leonard Guler ,  Souvik Chakrabarty ,  Jun Sung Kang ,  Bruce Beattie ,  Tahir Ghani

IPC: H01L29/06 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.

公开(公告)号：US12302632B2

公开(公告)日：2025-05-13

申请号：US18523637

申请日：2023-11-29

Applicant: Intel Corporation

Inventor： Jun Sung Kang ,  Kai Loon Cheong ,  Erica J. Thompson ,  Biswajeet Guha ,  William Hsu ,  Dax M. Crum ,  Tahir Ghani ,  Bruce Beattie

IPC: H10D84/85 ,  H10D30/01 ,  H10D30/62 ,  H10D62/10 ,  H10D62/832 ,  H10D64/01 ,  H10D64/27 ,  H10D64/68 ,  H10D84/01 ,  H10D84/03

Abstract: Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process are described. For example, an integrated circuit structure includes a fin or nanowire. A gate stack is over the fin or nanowire. The gate stack includes a gate dielectric and a gate electrode. A first dielectric spacer is along a first side of the gate stack, and a second dielectric spacer is along a second side of the gate stack. The first and second dielectric spacers are over at least a portion of the fin or nanowire. An insulating material is vertically between and in contact with the portion of the fin or nanowire and the first and second dielectric spacers. A first epitaxial source or drain structure is at the first side of the gate stack, and a second epitaxial source or drain structure is at the second side of the gate stack.