公开(公告)号：US20180190350A1

公开(公告)日：2018-07-05

申请号：US15396251

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： Christopher F. CONNOR ,  Bruce QUERBACH ,  Hanmant P. BELGAL

IPC: G11C13/00 ,  G06F3/06

CPC classification number: G11C13/004 ,  G06F3/0611 ,  G06F3/0634 ,  G06F3/0679 ,  G11C13/0004 ,  G11C13/0033 ,  G11C16/26 ,  G11C16/3418 ,  G11C2013/0052

Abstract: In one embodiment, a non-volatile memory is controlled in a selectable read mode in response to commands from a processor. Selectable read modes may include a default read memory mode, for example, and a performance read memory mode having a shorter read pulse and a reduced read latency than the default read memory mode, for example. In one embodiment, the performance read memory mode may also have refresh operations at an increased frequency compared to that of the default read mode. Other aspects and advantages are described.

公开(公告)号：US20190122729A1

公开(公告)日：2019-04-25

申请号：US16231126

申请日：2018-12-21

Applicant: INTEL CORPORATION

Inventor： Christopher F. CONNOR ,  Bruce QUERBACH ,  Hanmant P. BELGAL

IPC: G11C13/00 ,  G11C16/34 ,  G11C16/26 ,  G06F3/06

Abstract: In one embodiment, a non-volatile memory is controlled in a selectable read mode in response to commands from a processor. Selectable read modes may include a default read memory mode, for example, and a performance read memory mode having a shorter read pulse and a reduced read latency than the default read memory mode, for example. In one embodiment, the performance read memory mode may also have refresh operations at an increased frequency compared to that of the default read mode. Other aspects and advantages are described.