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    MEMORY REFRESH OPERATION WITH PAGE OPEN
    1.
    发明申请
    MEMORY REFRESH OPERATION WITH PAGE OPEN 审中-公开

    公开(公告)号：US20170236575A1

    公开(公告)日：2017-08-17

    申请号：US15585678

    申请日：2017-05-03

    Applicant: Intel Corporation

    Inventor： Bruce QUERBACH ,  Kuljit BAINS ,  John HALBERT

    IPC: G11C11/406 ,  G11C11/4094

    CPC classification number: G11C11/40618 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4096

    Abstract: Embodiments are generally directed to memory refresh operation with page open. An embodiment of a memory device includes a memory array including a plurality of memory banks; and a control logic to provide control operations for the memory device including a page open refresh mode, wherein the control logic is to perform a refresh cycle in response to a refresh command with a memory page of the memory array open, the refresh operation including precharge of one or more memory banks of the plurality of memory banks, refresh of the one or more memory banks, and activation of the memory page.

    EXTENDED PLATFORM WITH ADDITIONAL MEMORY MODULE SLOTS PER CPU SOCKET AND CONFIGURED FOR INCREASED PERFORMANCE
    4.
    发明申请
    EXTENDED PLATFORM WITH ADDITIONAL MEMORY MODULE SLOTS PER CPU SOCKET AND CONFIGURED FOR INCREASED PERFORMANCE 审中-公开

    公开(公告)号：US20180095909A1

    公开(公告)日：2018-04-05

    申请号：US15283186

    申请日：2016-09-30

    Applicant: INTEL CORPORATION

    Inventor： Bruce QUERBACH ,  Pete D. VOGT

    IPC: G06F13/16

    CPC classification number: G06F13/1678 ,  G06F1/18 ,  G06F13/1694 ,  G11C5/06

    Abstract: Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board (PCB) that includes a printed circuit board defining a length and a width, the length being greater than the width. The apparatus includes a first row of elements on thePCB, including a first memory region configured to receive at least one memory module. The apparatus includes a second row of elements on the PCB, including a first central processing unit (CPU) socket configured to receive a first CPU, and a second CPU socket configured to receive a second CPU, the first CPU socket and the second CPU socket positioned side by side along the width of the PCB. The apparatus also includes a third row of elements on the PCB, including a second memory region configured to receive a at least one memory module, wherein the second row of elements is positioned between the first row of elements and the third rows of elements. Other embodiments are described and claimed.

    MEMORY CONTROLLER-CONTROLLED REFRESH ABORT
    5.
    发明申请
    MEMORY CONTROLLER-CONTROLLED REFRESH ABORT 有权

    公开(公告)号：US20170352406A1

    公开(公告)日：2017-12-07

    申请号：US15174946

    申请日：2016-06-06

    Applicant: Intel Corporation

    Inventor： Bruce QUERBACH ,  Kuljit S. BAINS ,  John B. HALBERT

    IPC: G11C11/406 ,  G06F3/06 ,  G11C14/00

    CPC classification number: G11C11/40618 ,  G06F3/0604 ,  G06F3/0632 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/40622 ,  G11C14/0009

    Abstract: A memory subsystem enables a refresh abort command. A memory controller can issue an abort for an in-process refresh command sent to a memory device. The refresh abort enables the memory controller to more precisely control the timing of operations executed by memory devices in the case where a refresh command causes refresh of multiple rows of memory. The memory controller can issue a refresh command during active operation of the memory device, which is active operation refresh as opposed to self-refresh when the memory device controls refreshing. The memory controller can then issue a refresh abort during the refresh, and prior to completion of the refresh. The memory controller thus has deterministic control over both the start of refresh as well as when the memory device can be made available for access.

    EXTENDED PLATFORM WITH ADDITIONAL MEMORY MODULE SLOTS PER CPU SOCKET AND CONFIGURED FOR INCREASED PERFORMANCE
    7.
    发明申请
    EXTENDED PLATFORM WITH ADDITIONAL MEMORY MODULE SLOTS PER CPU SOCKET AND CONFIGURED FOR INCREASED PERFORMANCE 审中-公开

    公开(公告)号：US20190258594A1

    公开(公告)日：2019-08-22

    申请号：US16283597

    申请日：2019-02-22

    Applicant: Intel Corporation

    Inventor： Bruce QUERBACH ,  Pete D. VOGT

    IPC: G06F13/16 ,  G06F1/18

    Abstract: Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board (PCB) that includes a printed circuit board defining a length and a width, the length being greater than the width. The apparatus includes a first row of elements on the PCB, including a first memory region configured to receive at least one memory module. The apparatus includes a second row of elements on the PCB, including a first central processing unit (CPU) socket configured to receive a first CPU, and a second CPU socket configured to receive a second CPU, the first CPU socket and the second CPU socket positioned side by side along the width of the PCB. The apparatus also includes a third row of elements on the PCB, including a second memory region configured to receive a at least one memory module, wherein the second row of elements is positioned between the first row of elements and the third rows of elements. Other embodiments are described and claimed.

    SELF-HEALING IN A COMPUTING SYSTEM USING EMBEDDED NON-VOLATILE MEMORY
    8.
    发明申请
    SELF-HEALING IN A COMPUTING SYSTEM USING EMBEDDED NON-VOLATILE MEMORY 审中-公开

    公开(公告)号：US20190042351A1

    公开(公告)日：2019-02-07

    申请号：US15943594

    申请日：2018-04-02

    Applicant: Intel Corporation

    Inventor： Christopher CONNOR ,  Bruce QUERBACH

    IPC: G06F11/07 ,  G06F9/4401

    Abstract: Examples include techniques for self-healing of a processor in a computing system. A processor semiconductor chip includes one or more processing cores and an embedded non-volatile random-access memory (NVRAM), the NVRAM storing instructions that when executed by the one or more processing cores detect an error causing a core failure, update processor configuration information that reflects the core failure, and cause reset and initialization of the processor using the updated processor configuration information.

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