公开(公告)号：US11631595B2

公开(公告)日：2023-04-18

申请号：US17521406

申请日：2021-11-08

Applicant: Intel Corporation

Inventor： Sri Chaitra Jyotsna Chavali ,  Siddharth K. Alur ,  Lilia May ,  Amanda E. Schuckman

IPC: H01L21/48 ,  H01L23/498

Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.

公开(公告)号：US20170207152A1

公开(公告)日：2017-07-20

申请号：US15478064

申请日：2017-04-03

Applicant: Intel Corporation

Inventor： Thomas J. De Bonis ,  Lilia May ,  Rajen S. Sidhu ,  Mukul P. Renavikar ,  Ashay A. Dani ,  Edward R. Prack ,  Carl L. Deppisch ,  Anna M. Prakash ,  James C. Matayabas ,  Jason Jieping Zhang ,  Srinivasa R. Aravamudhan ,  Chang Lin

IPC: H01L23/498 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/76802 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13023 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/37001 ,  H01L2924/00

Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.

公开(公告)号：US12062551B2

公开(公告)日：2024-08-13

申请号：US18118835

申请日：2023-03-08

Applicant: Intel Corporation

Inventor： Sri Chaitra Jyotsna Chavali ,  Siddharth K. Alur ,  Lilia May ,  Amanda E. Schuckman

IPC: H01L21/48 ,  H01L23/498

CPC classification number: H01L21/4857 ,  H01L23/49822 ,  H01L23/49827

Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.

公开(公告)号：US11272619B2

公开(公告)日：2022-03-08

申请号：US16321420

申请日：2016-09-02

Applicant: INTEL CORPORATION

Inventor： Kristof Darmawikarta ,  Robert A. May ,  Yikang Deng ,  Ji Yong Park ,  Maroun D. Moussallem ,  Amruthavalli P. Alur ,  Sri Ranga Sai Boyapati ,  Lilia May

IPC: H05K1/18 ,  H05K3/42 ,  H01L21/60 ,  H01L27/146 ,  G01J5/20 ,  H05K1/11 ,  H05K3/46

Abstract: An apparatus is provided which comprises: a cavity made in a substrate of a printed circuit board (PCB); a plurality of solder balls embedded in the cavity; and a horizontal trace within the substrate, wherein the horizontal trace is partially directly under the plurality of solder balls and is coupled to the plurality of solder balls and another trace or via in the substrate such that a substrate region under the plurality of solder balls is independent of a stop layer under the cavity.

公开(公告)号：US10573622B2

公开(公告)日：2020-02-25

申请号：US15720480

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Lilia May ,  Edward R. Prack

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/50 ,  H01L23/538 ,  H01L23/31 ,  H01L25/10 ,  H01L21/60

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include forming a metal formate on a surface of a first solder interconnect structure disposed on a first package substrate at a first temperature, and attaching a second solder interconnect structure disposed on a second package substrate to the first solder interconnect structure at a second temperature. The second temperature decomposes at least a portion of the metal formate and generates a hydrogen gas. The generated hydrogen gas removes an oxide from the second solder interconnect structure during joint formation at the second temperature.

公开(公告)号：US10049971B2

公开(公告)日：2018-08-14

申请号：US15478064

申请日：2017-04-03

Applicant: Intel Corporation

Inventor： Thomas J. De Bonis ,  Lilia May ,  Rajen S. Sidhu ,  Mukul P. Renavikar ,  Ashay A. Dani ,  Edward R. Prack ,  Carl L. Deppisch ,  Anna M. Prakash ,  James C. Matayabas ,  Jason Jieping Zhang ,  Srinivasa R. Aravamudhan ,  Chang Lin

IPC: H01L21/00 ,  H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L25/00 ,  H01L23/00

Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.

公开(公告)号：US20220059367A1

公开(公告)日：2022-02-24

申请号：US17521406

申请日：2021-11-08

Applicant: Intel Corporation

Inventor： Sri Chaitra Jyotsna Chavali ,  Siddharth K. Alur ,  Lilia May ,  Amanda E. Schuckman

IPC: H01L21/48 ,  H01L23/498

Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.

公开(公告)号：US11195727B2

公开(公告)日：2021-12-07

申请号：US16901172

申请日：2020-06-15

Applicant: Intel Corporation

Inventor： Sri Chaitra Jyotsna Chavali ,  Siddharth K. Alur ,  Lilia May ,  Amanda E. Schuckman

IPC: H01L21/48 ,  H01L23/498

Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.

公开(公告)号：US20240329333A1

公开(公告)日：2024-10-03

申请号：US18129690

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Robert May ,  Bai Nie ,  Changhua Liu ,  Hiroki Tanaka ,  Kristof Darmawikarta ,  Lilia May ,  Shriya Seshadri ,  Srinivas Pietambaram ,  Tarek Ibrahim

IPC: G02B6/42 ,  G02B6/13 ,  H01L25/065 ,  H01L25/16

CPC classification number: G02B6/4202 ,  G02B6/13 ,  H01L25/0655 ,  H01L25/167 ,  G02B2006/12038

Abstract: Multi-die packages including both photonic and electric integrated circuit (IC) die interconnected to each other through a routing structure built-up on a glass substrate. A glass preform comprising an optical waveguide may also be attached to the routing structure. A plurality of electrical IC (EIC) die may be arrayed over the routing structure along with a plurality of photonic IC (PIC). Each PIC may be coupled to an optical waveguide within the glass preform. Conductive vias may extend through the glass substrate and be further coupled with a host substrate. The host substrate may comprise glass and an optical waveguide embedded within the glass. A vertical coupler may be attached to the host substrate to optically couple the host substrate to the optical waveguide within the glass preform of the multi-die package. Many of the multi-die packages may be arrayed over a routing structure on the host substrate.

公开(公告)号：US20240111090A1

公开(公告)日：2024-04-04

申请号：US17957341

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Robert A. May ,  Tarek Ibrahim ,  Shriya Seshadri ,  Kristof Darmawikarta ,  Hiroki Tanaka ,  Changhua Liu ,  Bai Nie ,  Lilia May ,  Srinivas Pietambaram ,  Zhichao Zhang ,  Duye Ye ,  Yosuke Kanaoka ,  Robin McRee

IPC: G02B6/12 ,  G02B6/13

CPC classification number: G02B6/12004 ,  G02B6/13 ,  G02B2006/12171

Abstract: A device comprises a substrate and an IC die, which may be a photonic IC. The substrate comprises a first surface, a second surface opposite the first surface, an optical waveguide integral with the substrate, and a hole extending from the first surface to the second surface. The hole comprises a first sidewall. The optical waveguide is between the first surface and the second surface, parallel to the first surface, and comprises a first end which extends to the first sidewall. The IC die is within the hole and comprises a second sidewall and an optical port at the second sidewall. The second sidewall is proximate to the first sidewall and the first end of the optical waveguide is proximate to and aligned with the optical port. The substrate may include a recess to receive another device comprising a socket.