公开(公告)号：US20250096053A1

公开(公告)日：2025-03-20

申请号：US18470645

申请日：2023-09-20

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Bohan Shan ,  Tarek A. Ibrahim ,  Srinivas V. Pietambaram ,  Gang Duan ,  Benjamin T. Duong ,  Suddhasattwa Nad

IPC: H01L23/15 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L25/065

Abstract: A microelectronic assembly includes an embedded bridge die and a glass structure, such as glass patch, under the bridge die. The bridge die and the glass structure are embedded in a substrate. The assembly may further include two or more dies arranged over the substrate and coupled to the bridge die. The glass structure may include through-glass vias, and vias in the substrate below the glass structure are self-aligned to the through-glass vias. The glass structure may include an embedded passive device, such as an embedded inductor or capacitor.

公开(公告)号：US20240395661A1

公开(公告)日：2024-11-28

申请号：US18202046

申请日：2023-05-25

Applicant: Intel Corporation

Inventor： Numair Ahmed ,  Suddhasattwa Nad ,  Mohammad Mamunur Rahman ,  Brandon C. Marin ,  Sashi S. Kandanur ,  Srinivas Venkata Ramanuja Pietambaram ,  Darko Grujicic ,  Gang Duan ,  Banjamin Duong

IPC: H01L23/473 ,  H01L23/31 ,  H01L23/373 ,  H01L23/48 ,  H01L23/498

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a glass core layer having a first surface layer and a second surface layer; multiple channels within the glass core layer between the first surface and the second surface layer; and a first redistribution layer (RDL) including multiple sublayers of conductive traces formed in an organic material, wherein a first surface of the RDL contacts the first surface of the glass core layer.

公开(公告)号：US12033930B2

公开(公告)日：2024-07-09

申请号：US17033392

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Jieying Kong ,  Yiyang Zhou ,  Suddhasattwa Nad ,  Jeremy Ecton ,  Hongxia Feng ,  Tarek Ibrahim ,  Brandon Marin ,  Zhiguo Qian ,  Sarah Blythe ,  Bohan Shan ,  Jason Steill ,  Sri Chaitra Jyotsna Chavali ,  Leonel Arana ,  Dingying Xu ,  Marcel Wall

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/485 ,  H01L23/49827

Abstract: An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.

公开(公告)号：US12027466B2

公开(公告)日：2024-07-02

申请号：US17026703

申请日：2020-09-21

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Aleksandar Aleksov ,  Brandon C. Marin ,  Yonggang Li ,  Leonel Arana ,  Suddhasattwa Nad ,  Haobo Chen ,  Tarek Ibrahim

IPC: H01L23/538 ,  H01L21/768 ,  H05K1/11

CPC classification number: H01L23/5386 ,  H01L21/76838 ,  H01L23/5385 ,  H05K1/11

Abstract: Conductive routes for an electronic substrate may be fabricated by forming an opening in a material, using existing laser drilling or lithography tools and materials, followed by selectively plating a metal on the sidewalls of the opening. The processes of the present description may result in significantly higher patterning resolution or feature scaling (up to 2× improvement in patterning density/resolution). In addition to improved patterning resolution, the embodiments of the present description may also result in higher aspect ratios of the conductive routes, which can result in improved signaling, reduced latency, and improved yield.

公开(公告)号：US20240194608A1

公开(公告)日：2024-06-13

申请号：US18080612

申请日：2022-12-13

Applicant: Intel Corporation

Inventor： Gang Duan ,  Rahul Manepalli ,  Srinivas Pietambaram ,  Brandon Marin ,  Suddhasattwa Nad ,  Jeremy Ecton

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5384 ,  H01L2221/68359

Abstract: An integrated circuit (IC) package comprises a first IC die having first metallization features, a second IC die having second metallization features, and a third IC die having third metallization features. A glass layer is between the third IC die and both of the first IC die and the second IC die. A plurality of first through vias extend through the glass layer, coupling the third metallization features with first ones of the first metallization features and with first ones of the second metallization features. A plurality of second through vias extend through the glass layer. A dielectric material is around the third die and a package metallization is within the dielectric material. The package metallization is coupled to at least one of the first, second, or third IC die, and terminating at a plurality of package interconnect interfaces.

公开(公告)号：US20240186250A1

公开(公告)日：2024-06-06

申请号：US18061188

申请日：2022-12-02

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Brandon Christian Marin ,  Srinivas V. Pietambaram ,  Tarek A. Ibrahim ,  Suddhasattwa Nad ,  Gang Duan ,  Haobo Chen ,  Hiroki Tanaka

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L23/5384 ,  H01L23/5386

Abstract: A microelectronic assembly includes a substrate comprising: a panel including glass and defining an opening therein; an interconnect bridge (IB) in the opening and including interconnect pathways and IB through vias (IBTVs); and electrically conductive structures at a lower surface of the substrate to electrically couple the substrate to another component, at least some of the electrically conductive structures coupled to the IBTVs to form respective vertical electrical connections between the lower surface of the substrate and an upper surface of the substrate; and an electronic component (EC) layer on the upper surface of the substrate, the EC layer including a first active EC (AEC) and a second AEC electrically coupled to one another through the interconnect pathways, at least one of the first AEC or the second AECs further electrically coupled to one or more of the at least some of the electrically conductive structures.

公开(公告)号：US20240079339A1

公开(公告)日：2024-03-07

申请号：US17929045

申请日：2022-09-01

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Gang Duan ,  Benjamin T. Duong ,  Suddhasattwa Nad ,  Jeremy Ecton

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L21/4846 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0652 ,  H01L23/481 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253

Abstract: Embodiments of a microelectronic assembly comprise: a package substrate including a first integrated circuit (IC) die embedded therein; and a second IC die coupled to the package substrate and conductively coupled to the first IC die by vias in the package substrate. The package substrate has a first side and an opposing second side, the second IC die is coupled to the first side of the package substrate, the first IC die is between the first side of the package substrate and the second side of the package substrate, the package substrate comprises a plurality of layers of conductive traces in an organic dielectric material, the first IC die is surrounded by the organic dielectric material of the package substrate, the vias are in the organic dielectric material between the first IC die and the first side of the package substrate, and the first IC die comprises through-substrate vias.

公开(公告)号：US20240079335A1

公开(公告)日：2024-03-07

申请号：US17939824

申请日：2022-09-07

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Brandon Christian Marin ,  Srinivas V. Pietambaram ,  Gang Duan ,  Suddhasattwa Nad

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/08 ,  H01L25/0655 ,  H01L2224/08225

Abstract: In one embodiment, an integrated circuit device includes a first layer having input/output (IO) hub circuitry to interconnect a plurality of integrated circuit dies, and a second layer having a plurality of integrated circuit dies electrically connected to the IO hub circuitry. The first layer may include glass, and the IO hub circuitry may be in a die embedded within the first layer. The integrated circuit dies may be electrically connected to the IO hub circuitry through an interposer.

公开(公告)号：US20240006285A1

公开(公告)日：2024-01-04

申请号：US17855662

申请日：2022-06-30

Applicant: The Intel Corporation

Inventor： Yi Yang ,  Suddhasattwa Nad ,  Xiaoying Guo ,  Jieying Kong ,  Ala Omer ,  Christy Sennavongsa ,  Wei Wei ,  Ao Wang

IPC: H01L23/498 ,  H01L23/14 ,  H01L21/48 ,  H05K1/11 ,  H05K3/40 ,  H05K3/22

CPC classification number: H01L23/49822 ,  H01L23/145 ,  H01L23/49866 ,  H01L21/4857 ,  H05K1/115 ,  H05K3/4038 ,  H05K3/22 ,  H01L2224/16227 ,  H01L24/16

Abstract: Substrate assemblies having adhesion promotor layers and related methods are disclosed. An example apparatus includes a substrate, a dielectric layer, a first copper layer between the substrate and the dielectric layer, and a film between the dielectric layer and the first copper layer. The film including silicon and nitrogen and being substantially free of hydrogen. A via in the dielectric layer is to provide access to the first copper layer. A portion of the first copper layer uncovered in the via, a wall of the via and the portion of the first copper layer to be substantially free of fluorine. A seed copper layer positioned on the dielectric layer. The via wall and the portion of the first copper layer. The seed copper layer and the first copper layer define an undercut at an interface between the seed copper layer and the first copper layer.

公开(公告)号：US20230402368A1

公开(公告)日：2023-12-14

申请号：US17837732

申请日：2022-06-10

Applicant: Intel Corporation

Inventor： Benjamin T. Duong ,  Brian P. Balch ,  Kristof Darmawikarta ,  Darko Grujicic ,  Suddhasattwa Nad ,  Xing Sun ,  Marcel A. Wall ,  Yi Yang

IPC: H01L23/522 ,  H01C7/00 ,  H01L49/02

CPC classification number: H01L23/5228 ,  H01L28/24 ,  H01L23/5226 ,  H01C7/006

Abstract: Techniques for thin-film resistors in vias are disclosed. In the illustrative embodiment, thin-film resistors are formed in through-glass vias of a glass substrate of an interposer. The thin-film resistors do not take up a significant amount of area on a layer of the interposer, as the thin-film resistor extends vertically through a via rather than horizontally on a layer of the interposer. The thin-film resistors may be used for any suitable purpose, such as power dissipation or voltage control, current control, as a pull-up or pull-down resistor, etc.