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    STACKED MEMROY LAYERS WITH GLOBAL BIT LINE OR GLOBAL WORD LINE
    3.
    发明申请
    STACKED MEMROY LAYERS WITH GLOBAL BIT LINE OR GLOBAL WORD LINE 有权

    公开(公告)号：US20250104760A1

    公开(公告)日：2025-03-27

    申请号：US18471382

    申请日：2023-09-21

    Applicant: Intel Corporation

    Inventor： Abhishek A. Sharma ,  Sagar Suthram ,  Wilfred Gomes ,  Anand S. Murthy ,  Tahir Ghani ,  Pushkar Sharad Ranade

    IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4094

    Abstract: An IC device may include memory layers over a logic layer. A memory layer includes memory arrays, each of which includes memory cells arranged in rows and columns. A row of memory cells may be associated with a word line. A column of memory cells may be associated with a bit line. Bit lines of different memory arrays may be coupled using one or more vias or source/drain electrodes of transistors in the memory arrays. Alternatively, word lines of different memory arrays may be coupled using one or more vias or gate electrodes of transistors in the memory arrays. The logic layer has a logic circuit that can control data read operations and data write operations of the memory layers. The logic layer may include a power interconnect, which facilitates power delivery to the memory layers, and a signal interconnect, which facilitates signal transmission within the memory device.

    MEMORY CELL WITH TRANSISTOR HAVING INCREASED LEAKAGE CURRENT
    6.
    发明申请
    MEMORY CELL WITH TRANSISTOR HAVING INCREASED LEAKAGE CURRENT 有权

    公开(公告)号：US20240431092A1

    公开(公告)日：2024-12-26

    申请号：US18338440

    申请日：2023-06-21

    Applicant: Intel Corporation

    Inventor： Abhishek A. Sharma ,  Wilfred Gomes ,  Tahir Ghani ,  Anand S. Murthy

    IPC: H10B12/00

    Abstract: A transistor may include a source region, a drain region, a channel region between the source region and the drain region in a first direction, a gate electrode, a source contact, and a drain contact. A first portion of the gate electrode is over the channel region in a second direction substantially perpendicular to the first direction. A second portion of the gate electrode is over a first portion of the drain region in the second direction. The source contact is over at least part of the source region. The drain contact is over a second portion of the drain region. A distance from an edge of the first portion of the drain region to an edge of the gate electrode or to an edge the first trench electrode in the first direction is greater than a fourth of a length of the gate electrode in the first direction.

    Integrated circuit assemblies with direct chip attach to circuit boards
    7.
    发明授权
    Integrated circuit assemblies with direct chip attach to circuit boards 有权

    公开(公告)号：US12170273B2

    公开(公告)日：2024-12-17

    申请号：US17210682

    申请日：2021-03-24

    Applicant: Intel Corporation

    Inventor： Wilfred Gomes ,  Sanka Ganesan ,  Abhishek A. Sharma ,  Doug B. Ingerly ,  Mauro J. Kobrinsky ,  Kevin Fischer

    IPC: H01L25/18 ,  H01L23/00 ,  H01L23/12 ,  H01L23/528 ,  H01L23/538 ,  H01L25/065

    Abstract: Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages, related to direct chip attach of dies and circuit boards. An example microelectronic assembly includes a die with IC components provided over the die's frontside, and a metallization stack provided over the die's backside. The die further includes die interconnects extending between the frontside and the backside of the die, to electrically couple the IC components and the metallization stack. The assembly further includes backside conductive contacts, provided over the side of the metallization stack facing away from the die, the backside conductive contacts configured to route signals to/from the IC components via the metallization stack and the die interconnects, and configured to be coupled to respective conductive contacts of a circuit board in absence of a package substrate between the die and the circuit board.

    Hyperchip
    9.
    发明授权
    Hyperchip 有权

    公开(公告)号：US11984430B2

    公开(公告)日：2024-05-14

    申请号：US18128958

    申请日：2023-03-30

    Applicant: Intel Corporation

    Inventor： Mark T. Bohr ,  Wilfred Gomes ,  Rajesh Kumar ,  Pooya Tadayon ,  Doug Ingerly

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538

    CPC classification number: H01L25/0655 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/13 ,  H01L2225/06541

    Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

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