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公开(公告)号：US09848344B2
公开(公告)日：2017-12-19
申请号：US15630444
申请日：2017-06-22
Applicant: InterDigital Technology Corporation
Inventor： Allan Y. Tsai , William E. Lawton , Lakshmi R. Iyer , Muhammad U. Fazili , Manasa Raghavan
CPC classification number: H04W24/02 , H04B17/336 , H04L5/005 , H04L7/02 , H04L27/265 , H04L27/3494 , H04M2207/206 , H04W28/0236 , H04W52/12 , H04W56/0035
Abstract: Disclosed are embodiments of apparatuses and methods of use thereof for frequency domain (FD) chip level (CL) equalizers used in wireless receivers. The FD-CL-EQ may further selectively apply a higher order matrix inverse or a lower order matrix inverse in the calculation of a channel estimate based on whether interference is present or not. Further disclosed are embodiments of methods and apparatuses for estimating pilot signal-to-interference ratio (SIR) in the wireless receivers. Further disclosed are methods and apparatuses for compensating for phase errors in received demodulated data symbols to improve performance of the wireless receivers.
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公开(公告)号：US20160353293A1
公开(公告)日：2016-12-01
申请号：US15169100
申请日：2016-05-31
Applicant: INTERDIGITAL TECHNOLOGY CORPORATION
Inventor： Allan Y. Tsai , William E. Lawton , Lakshmi R. Iyer , Muhammad U. Fazili , Manasa Raghavan
IPC: H04W24/02 , H04B17/336 , H04L27/34 , H04W72/04 , H04L27/26 , H04W56/00 , H04L12/26 , H04L5/00 , H04W28/02
CPC classification number: H04W24/02 , H04B17/336 , H04L5/005 , H04L7/02 , H04L27/265 , H04L27/3494 , H04M2207/206 , H04W28/0236 , H04W52/12 , H04W56/0035
Abstract: Disclosed are embodiments of apparatuses and methods of use thereof for frequency domain (FD) chip level (CL) equalizers used in wireless receivers. The FD-CL-EQ may further selectively apply a higher order matrix inverse or a lower order matrix inverse in the calculation of a channel estimate based on whether interference is present or not. Further disclosed are embodiments of methods and apparatuses for estimating pilot signal-to-interference ratio (SIR) in the wireless receivers. Further disclosed are methods and apparatuses for compensating for phase errors in received demodulated data symbols to improve performance of the wireless receivers.
Abstract translation: 公开了用于无线接收机中的频域（FD）芯片级（CL）均衡器的装置及其使用方法的实施例。 基于是否存在干扰，FD-CL-EQ还可以在信道估计的计算中进一步选择性地应用更高阶矩阵逆或低阶矩阵逆。 进一步公开的是用于估计无线接收机中的导频信号干扰比（SIR）的方法和装置的实施例。 还公开了用于补偿接收的解调数据符号中的相位误差以提高无线接收机的性能的方法和装置。
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Patent Agency Ranking
公开(公告)号：US20160337105A1
公开(公告)日：2016-11-17
申请号：US15156148
申请日：2016-05-16
Applicant: INTERDIGITAL TECHNOLOGY CORPORATION
Inventor： William E. Lawton , Manasa Raghavan , Lakshmi R. Iyer , Muhammad U. Fazili , Louis E. Pouliot , Allan Y. Tsai , Alpaslan Demir , Shane S. Supplee
CPC classification number: H04L5/0057 , H04B7/0619 , H04B17/309 , H04B17/336 , H04L1/0026 , H04L1/0028 , H04L5/0007 , H04L25/0232
Abstract: Systems, methods, and instrumentalities for a WTRU to perform channel estimation and/or noise estimation are provided. The techniques described herein may be used to perform channel estimation and/or noise estimation that meet certain performance and latency goals while utilizing a lower cost design than previous channel/noise estimation techniques. For example, the channel estimation/noise estimation techniques described herein may be implemented using less memory (e.g., less memory for storing filter coefficients) while still achieving the desired latency and performance goals. The techniques described herein may be implemented by any WTRU and/or by a WTRU specifically designed to be low-cost.
Abstract translation: 提供了WTRU执行信道估计和/或噪声估计的系统，方法和手段。 本文描述的技术可以用于执行符合某些性能和延迟目标的信道估计和/或噪声估计，同时使用比先前的信道/噪声估计技术更低的成本设计。 例如，本文描述的信道估计/噪声估计技术可以使用更少的存储器（例如，用于存储滤波器系数的较少存储器）来实现，同时仍然实现期望的延迟和性能目标。 本文描述的技术可以由任何WTRU和/或由专门设计成低成本的WTRU来实现。
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公开(公告)号：US10039017B2
公开(公告)日：2018-07-31
申请号：US15845510
申请日：2017-12-18
Applicant: InterDigital Technology Corporation
Inventor： Allan Y. Tsai , William E. Lawton , Lakshmi R. Iyer , Muhammad U. Fazili , Manasa Raghavan
CPC classification number: H04W24/02 , H04B17/336 , H04L5/0051 , H04L5/0057 , H04L7/02 , H04L27/2331 , H04L27/265 , H04L27/34 , H04M2207/206 , H04W28/0236 , H04W52/12 , H04W56/0035
Abstract: Disclosed are embodiments of apparatuses and methods of use thereof for frequency domain (FD) chip level (CL) equalizers used in wireless receivers. The FD-CL-EQ may further selectively apply a higher order matrix inverse or a lower order matrix inverse in the calculation of a channel estimate based on whether interference is present or not. Further disclosed are embodiments of methods and apparatuses for estimating pilot signal-to-interference ratio (SIR) in the wireless receivers. Further disclosed are methods and apparatuses for compensating for phase errors in received demodulated data symbols to improve performance of the wireless receivers.
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公开(公告)号：US20180109965A1
公开(公告)日：2018-04-19
申请号：US15845510
申请日：2017-12-18
Applicant: InterDigital Technology Corporation
Inventor： Allan Y. Tsai , William E. Lawton , Lakshmi R. Iyer , Muhammad U. Fazili , Manasa Raghavan
CPC classification number: H04W24/02 , H04B17/336 , H04L5/005 , H04L7/02 , H04L27/265 , H04L27/3494 , H04M2207/206 , H04W28/0236 , H04W52/12 , H04W56/0035
Abstract: Disclosed are embodiments of apparatuses and methods of use thereof for frequency domain (FD) chip level (CL) equalizers used in wireless receivers. The FD-CL-EQ may further selectively apply a higher order matrix inverse or a lower order matrix inverse in the calculation of a channel estimate based on whether interference is present or not. Further disclosed are embodiments of methods and apparatuses for estimating pilot signal-to-interference ratio (SIR) in the wireless receivers. Further disclosed are methods and apparatuses for compensating for phase errors in received demodulated data symbols to improve performance of the wireless receivers.
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公开(公告)号：US20170303147A1
公开(公告)日：2017-10-19
申请号：US15630444
申请日：2017-06-22
Applicant: InterDigital Technology Corporation
Inventor： Allan Y. Tsai , William E. Lawton , Lakshmi R. Iyer , Muhammad U. Fazili , Manasa Raghavan
CPC classification number: H04W24/02 , H04B17/336 , H04L5/005 , H04L7/02 , H04L27/265 , H04L27/3494 , H04M2207/206 , H04W28/0236 , H04W52/12 , H04W56/0035
Abstract: Disclosed are embodiments of apparatuses and methods of use thereof for frequency domain (FD) chip level (CL) equalizers used in wireless receivers. The FD-CL-EQ may further selectively apply a higher order matrix inverse or a lower order matrix inverse in the calculation of a channel estimate based on whether interference is present or not. Further disclosed are embodiments of methods and apparatuses for estimating pilot signal-to-interference ratio (SIR) in the wireless receivers. Further disclosed are methods and apparatuses for compensating for phase errors in received demodulated data symbols to improve performance of the wireless receivers.
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公开(公告)号：US09693240B2
公开(公告)日：2017-06-27
申请号：US15169100
申请日：2016-05-31
Applicant: INTERDIGITAL TECHNOLOGY CORPORATION
Inventor： Allan Y. Tsai , William E. Lawton , Lakshmi R. Iyer , Muhammad U. Fazili , Manasa Raghavan
CPC classification number: H04W24/02 , H04B17/336 , H04L5/005 , H04L7/02 , H04L27/265 , H04L27/3494 , H04M2207/206 , H04W28/0236 , H04W52/12 , H04W56/0035
Abstract: Disclosed are embodiments of apparatuses and methods of use thereof for frequency domain (FD) chip level (CL) equalizers used in wireless receivers. The FD-CL-EQ may further selectively apply a higher order matrix inverse or a lower order matrix inverse in the calculation of a channel estimate based on whether interference is present or not. Further disclosed are embodiments of methods and apparatuses for estimating pilot signal-to-interference ratio (SIR) in the wireless receivers. Further disclosed are methods and apparatuses for compensating for phase errors in received demodulated data symbols to improve performance of the wireless receivers.
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