WIRELESS TEST SYSTEM
    2.
    发明申请
    WIRELESS TEST SYSTEM 有权
    无线测试系统

    公开(公告)号:US20070210822A1

    公开(公告)日:2007-09-13

    申请号:US11749004

    申请日:2007-05-15

    CPC classification number: G01R31/3025 G01R31/31907 G01R31/31908

    Abstract: One or more testers wirelessly communicate with one or more test stations. The wireless communication may include transmission of test commands and/or test vectors to a test station, resulting in testing of one or more electronic devices at the test station. The wireless communication may also include transmission of test results to a tester. Messages may also be wirelessly exchanged.

    Abstract translation: 一个或多个测试人员与一个或多个测试台无线通信。 无线通信可以包括将测试命令和/或测试向量发送到测试站,导致测试台上的一个或多个电子设备的测试。 无线通信还可以包括将测试结果传输给测试者。 消息也可以被无线地交换。

    Methods for making plated through holes usable as interconnection wire or probe attachments

    公开(公告)号:US20060185164A1

    公开(公告)日:2006-08-24

    申请号:US11403138

    申请日:2006-04-11

    Abstract: Methods are provided for making plated through holes usable for inserting and attaching connector probes. In a first method, a curved plated through hole is formed by bonding curved etchable wires to a first substrate, plating the wires with a non-etchable conductive material, encasing the plated wires with a dielectric material to form a second substrate, planing the second substrate to expose the etchable wire, and etching the wires to leave plated through holes. In a second method, wires coated with a first etchable layer are initially bonded to a substrate, a second non-etchable plating layer is then applied over the first layer, and the first layer is etched away leaving plated through holes with wires disposed inside. In a third embodiment, a layer of masking material is initially deposited on a substrate and etched to form holes which are filled with a sacrificial fill material, the masking material is then removed, the fill material plated, grinding is performed to remove some plating to expose the fill material, and the fill material is then etched away leaving plated attachment wells. Probes may be attached to the plated through holes or attachment wells to create resilient spring contacts to form a wafer probe card assembly. A twisted tube plated through hole structure is formed by supporting twisted sacrificial wires coated with the plating material in a substrate, and later etching away the wires.

    Methods for making vertical electric feed through structures usable to form removable substrate tiles in a wafer test system
    5.
    发明申请
    Methods for making vertical electric feed through structures usable to form removable substrate tiles in a wafer test system 审中-公开
    用于通过可用于在晶片测试系统中形成可移除衬底砖的结构的垂直供电的方法

    公开(公告)号:US20050108875A1

    公开(公告)日:2005-05-26

    申请号:US10723263

    申请日:2003-11-26

    Abstract: Methods are provided for making vertical feed through electrical connection structures in a substrate or tile. The vertical feed throughs are configured to make the tile attachable and detachable as a layer between other substrates. For example, the tile with vertical feedthroughs can form an easily detachable space transformer tile in a wafer test system. The vertical feed through paths are formed with one end of each feed through hole permanently encapsulating a first electrical contact, and a second end supporting another pluggable and unpluggable electrical probe contact. Decoupling capacitors can be further plugged into holes formed in close proximity to the vertical feed through holes to increase performance of the decoupling capacitor.

    Abstract translation: 提供了用于通过基底或瓦片中的电连接结构进行垂直馈送的方法。 垂直进料通道被配置成使得瓦片能够作为其它基底之间的层附着和拆卸。 例如,具有垂直馈通的瓦片可以在晶片测试系统中形成容易拆卸的空间变压器瓦片。 垂直进料通道形成有每个进料通孔的一端,其永久地密封第一电接触,第二端支撑另一可插拔和可拔出的电探针接触。 去耦电容器可以进一步插入靠近垂直馈通孔形成的孔中,以提高去耦电容的性能。

    WAFER-LEVEL BURN-IN AND TEST
    7.
    发明申请
    WAFER-LEVEL BURN-IN AND TEST 失效
    WAFER-LEVEL BURN-IN和TEST

    公开(公告)号:US20070013401A1

    公开(公告)日:2007-01-18

    申请号:US11458375

    申请日:2006-07-18

    Abstract: Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate having active electronic components such as ASICs mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. The spring contact elements may be mounted to either the DUTs or to the ASICs, and may fan out to relax tolerance constraints on aligning and interconnecting the ASICs and the DUTs. Physical alignment techniques are also described.

    Abstract translation: 用于执行半导体器件的晶片级老化和测试的技术包括具有有源电子部件的测试基板,例如安装到互连基板或并入其中的ASIC,实现ASIC和多个器件之间的互连的金属弹簧接触元件 在测试晶片(WUT)上的测试(DUT)都被置于真空容器中,使得ASIC可以在与DUT的老化温度无关并且显着低于DUT的老化温度的温度下工作。 弹簧接触元件可以被安装到DUT或ASIC上,并且可以扇出来放松对ASIC和DUT的对准和互连的容限约束。 还描述了物理对准技术。

    Special contact points for accessing internal circuitry of an intergrated circuit
    9.
    发明申请
    Special contact points for accessing internal circuitry of an intergrated circuit 审中-公开
    用于访问集成电路内部电路的特殊接点

    公开(公告)号:US20060006384A1

    公开(公告)日:2006-01-12

    申请号:US11221231

    申请日:2005-09-06

    Abstract: One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads. The special contact points may also be used to externally program internal circuits (e.g., nonvolatile circuits) at the die or package level. The special contact points may also be used to select redundant circuits for faulty circuits.

    Abstract translation: 本发明的一个实施例涉及包括接合焊盘和特殊接触焊盘或点的集成电路。 接合焊盘用于将集成电路作为整体与外部电路接口,并且将被连接到封装或电路板。 接合焊盘以预定的对准方式设置在管芯上,例如外围,栅格或中心对准。 特殊接触焊盘用于向内部电路提供外部测试模式和/或外部监测测试内部电路的结果。 特别的接触垫可以有利地以高度的位置自由度位于集成电路上。 对于一个实施例,特殊接触焊盘可以在与焊盘不同于对准的位置处设置在管芯上。 特殊的接触焊盘可以小于接合焊盘,以便不会由于特殊的接触垫而增加管芯的尺寸。 特殊接触点也可以用于在芯片或封装级别外部编程内部电路(例如非易失性电路)。 特殊接触点也可用于选择故障电路的冗余电路。

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