公开(公告)号：US20210294949A1

公开(公告)日：2021-09-23

申请号：US17207030

申请日：2021-03-19

Applicant: Imagination Technologies Limited

Inventor： Simon Gaulter ,  Thomas Ferrere ,  Faizan Nazar ,  Sam Elliott

IPC: G06F30/33

Abstract: Methods and systems of verifying a hardware design for a sorter are disclosed. The methods include generating a modified version of the hardware design of the sorter accepting extended inputs and performing formal verification comprising: implementing a constraint that the least significant bits of each input in a set of extended inputs represent a unique value; and formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.

公开(公告)号：US12299412B2

公开(公告)日：2025-05-13

申请号：US17404868

申请日：2021-08-17

Applicant: Imagination Technologies Limited

Inventor： Thomas Ferrere

IPC: G06F7/485 ,  G06F5/01 ,  G06F7/499

Abstract: A method and system for processing a set of ‘k’ floating point numbers to perform addition and/or subtraction is disclosed. Each floating-point number comprises a mantissa (mi) and an exponent (ei). The method comprises receiving the set of ‘k’ floating point numbers in a first format, each floating-point number in the first format comprising a mantissa (mi) with a bit-length of ‘b’ bits. The method further comprises creating a set of ‘k’ numbers (yi) based on the mantissas of the ‘k’ floating-point numbers, the numbers having a bit-length of ‘n’ bits obtained by adding both extra most-significant bits and extra least-significant bits to the bit length ‘b’ of the mantissa (mi). The method includes identifying a maximum exponent (emax) among the exponents ei, aligning the magnitude bits of the numbers (yi) based on the maximum exponent (emax) and processing the set of ‘k’ numbers concurrently.

公开(公告)号：US20230334117A1

公开(公告)日：2023-10-19

申请号：US18111033

申请日：2023-02-17

Applicant: Imagination Technologies Limited

Inventor： Thomas Ferrere

IPC: G06F17/16 ,  G06F7/483

CPC classification number: G06F17/16 ,  G06F7/483

Abstract: A method of performing dot product of an array of ‘2k’ floating point numbers comprising two sets of k floating-point numbers ai and bi is disclosed. The method includes receiving both sets of ‘k’ floating point numbers and multiplying each floating point number ai with a floating point number bi to generate k product numbers (zi), each product number (zi) having a mantissa bit length of ‘r’ bits. The method further comprises creating a set of ‘k’ numbers (yi) based on the k product numbers (zi), the numbers (yi) having a bit-length of ‘n’ bits. Further the method includes identifying a maximum exponent sum (emax) among k exponent sums (eabi) of each pair of floating point numbers ai and bi, aligning the magnitude bits of the numbers (yi) based on the maximum exponent sum (emax) and adding the set of ‘k’ numbers concurrently to obtain the dot product.

公开(公告)号：US20250165219A1

公开(公告)日：2025-05-22

申请号：US18933060

申请日：2024-10-31

Applicant: Imagination Technologies Limited

Inventor： Kenneth Rovers ,  Max Freiburghaus ,  Thomas Ferrere

IPC: G06F7/499

Abstract: A method of rounding a floating-point number in an Extended Exponent Range (EER), that would be a denormal floating-point number represented in an Unextended Exponent Range (UER) includes the steps of receiving, at an arithmetic unit, a plurality of input numbers in the EER representation, each input number comprising a sign bit (si), exponent bits (ei) and mantissa bits (mi); performing an arithmetic operation to produce an output number in the EER representation comprising a sign bit (sa), an exponent bits (ea) and mantissa bits (ma); constructing a rounding mask based on the exponent bits (ea) computed by the arithmetic operation; and applying the rounding mask to the output number in the EER representation to round the output number to correct position as if rounding in the UER representation.

公开(公告)号：US20240037303A1

公开(公告)日：2024-02-01

申请号：US18377746

申请日：2023-10-06

Applicant: Imagination Technologies Limited

Inventor： Simon Gaulter ,  Thomas Ferrere ,  Faizan Nazar ,  Sam Elliott

IPC: G06F30/33

CPC classification number: G06F30/33

Abstract: Methods and systems of verifying a hardware design for a sorter are disclosed. The methods include generating a modified version of the hardware design of the sorter accepting extended inputs and performing formal verification comprising: implementing a constraint that the least significant bits of each input in a set of extended inputs represent a unique value; and formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.

公开(公告)号：US20230333812A1

公开(公告)日：2023-10-19

申请号：US18111178

申请日：2023-02-17

Applicant: Imagination Technologies Limited

Inventor： Thomas Ferrere

IPC: G06F7/487 ,  G06F17/16

CPC classification number: G06F7/4876 ,  G06F17/16

Abstract: A method of performing dot product of an array of ‘2k’ floating point numbers comprising two sets of k floating-point numbers ai and bi is disclosed. The method includes receiving both sets of ‘k’ floating point numbers and multiplying each floating point number ai with a floating point number bi to generate k product numbers (zi), each product number (zi) having a mantissa bit length of ‘r+log (k−1)+1’ bits. The method further comprises creating a set of ‘k’ numbers (yi) based on the k product numbers (zi), the numbers (yi) having a bit-length of ‘n’ bits. Further the method includes identifying a maximum exponent sum (emax) among k exponent sums (eabi) of each pair of floating point numbers ai and bi aligning the magnitude bits of the numbers (yi) based on the maximum exponent sum (emax) and adding the set of ‘k’ numbers concurrently to obtain the dot product.

公开(公告)号：US11783105B2

公开(公告)日：2023-10-10

申请号：US17207030

申请日：2021-03-19

Applicant: Imagination Technologies Limited

Inventor： Simon Gaulter ,  Thomas Ferrere ,  Faizan Nazar ,  Sam Elliott

IPC: G06F30/30 ,  G06F30/33

CPC classification number: G06F30/33

Abstract: Methods and systems of verifying a hardware design for a sorter are disclosed. The methods include generating a modified version of the hardware design of the sorter accepting extended inputs and performing formal verification comprising: implementing a constraint that the least significant bits of each input in a set of extended inputs represent a unique value; and formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.