公开(公告)号：US12062589B2

公开(公告)日：2024-08-13

申请号：US17361823

申请日：2021-06-29

Applicant: Infineon Technologies AG

Inventor： Adrian Lis ,  Michael Ledutke

IPC: H05K1/11 ,  H01L21/48 ,  H01L23/367 ,  H01L23/373 ,  H01L23/42 ,  H05K7/14

CPC classification number: H01L23/3675 ,  H01L21/4871 ,  H01L23/3735 ,  H01L23/42

Abstract: One example of a semiconductor package includes a first substrate, a second substrate, a semiconductor die, and a spacer. The semiconductor die is attached to the first substrate. The spacer is attached to the semiconductor die and attached to the second substrate via solder. A surface of the second substrate facing the spacer includes a plurality of recesses extending from proximate at least one edge of the spacer to contain a portion of the solder.

公开(公告)号：US20250096069A1

公开(公告)日：2025-03-20

申请号：US18816500

申请日：2024-08-27

Applicant: Infineon Technologies AG

Inventor： Adrian Lis ,  Thomas Schmid ,  Ewald Günther

IPC: H01L23/373 ,  H01L23/31 ,  H01L23/367 ,  H01L23/50 ,  H02M1/32

Abstract: A power module includes a substrate, one or more semiconductor dies mounted to the substrate, a first external power connection electrically connected to a first power terminal of at least one of the one or more semiconductor dies, and an encapsulant at least partially encapsulating the first external power connection. A portion of the first external power connection and at least parts of an outer surface of the substrate are exposed from the encapsulant. A heatsink is mounted to the first external power connection.

公开(公告)号：US12183667B2

公开(公告)日：2024-12-31

申请号：US17579727

申请日：2022-01-20

Applicant: Infineon Technologies AG

Inventor： Peter Scherl ,  Adrian Lis ,  Christian Neugirg

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package includes a first power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the first power electronics carrier, and a first pair of metal pads that are immediately laterally adjacent one another and are low-voltage difference nodes of the semiconductor package, a second pair of metal pads that are immediately laterally adjacent one another and are high-voltage difference nodes of the semiconductor package, and an encapsulant body of electrically insulating material that encapsulates the power semiconductor die and the first and second pairs of metal pads, wherein the first pair of the metal pads are laterally isolated from one another by a first minimum separation distance, and wherein the second pair of the metal pads are laterally isolated from one another by a second minimum separation distance that is greater than the first minimum separation distance.

公开(公告)号：US20230245968A1

公开(公告)日：2023-08-03

申请号：US17579727

申请日：2022-01-20

Applicant: Infineon Technologies AG

Inventor： Peter Scherl ,  Adrian Lis ,  Christian Neugirg

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/49844 ,  H01L21/565 ,  H01L21/4857 ,  H01L23/3107 ,  H01L23/49822 ,  H01L23/49833

Abstract: A semiconductor package includes a first power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the first power electronics carrier, and a first pair of metal pads that are immediately laterally adjacent one another and are low-voltage difference nodes of the semiconductor package, a second pair of metal pads that are immediately laterally adjacent one another and are high-voltage difference nodes of the semiconductor package, and an encapsulant body of electrically insulating material that encapsulates the power semiconductor die and the first and second pairs of metal pads, wherein the first pair of the metal pads are laterally isolated from one another by a first minimum separation distance, and wherein the second pair of the metal pads are laterally isolated from one another by a second minimum separation distance that is greater than the first minimum separation distance.

公开(公告)号：US12224222B2

公开(公告)日：2025-02-11

申请号：US17572858

申请日：2022-01-11

Applicant: Infineon Technologies AG

Inventor： Christian Neugirg ,  Adrian Lis ,  Peter Scherl ,  Ewald Guenther

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes: a first substrate having a first metallized side; a semiconductor die attached to the first metallized side of the first substrate at a first side of the die, a second side of the die opposite the first side being covered by a passivation, the passivation having a first opening that exposes at least part of a first pad at the second side of the die; a thermally and electrically conductive spacer attached to the part of the first pad that is exposed by the first opening in the passivation, the spacer at least partly overhanging the passivation along at least one side face of the semiconductor die; a second substrate having a first metallized side attached to the spacer at an opposite side of the spacer as the semiconductor die; and an encapsulant encapsulating the semiconductor die and the spacer. Additional spacer embodiments are described.

公开(公告)号：US20240413118A1

公开(公告)日：2024-12-12

申请号：US18332858

申请日：2023-06-12

Applicant: Infineon Technologies AG

Inventor： Peter Scherl ,  Adrian Lis

IPC: H01L23/00 ,  H05K1/02 ,  H05K1/18

Abstract: A power module is disclosed herein. In one embodiment, the power modules includes a solder repellent structure that adjoins a metallic surface of a substrate outside a perimeter of an electronic component attached to the metallic surface of the substrate and positioned adjacent to one or more sides of the electronic component, the solder repellent structure being configured to repel molten solder. In another embodiment, the power modules includes a solder wetting structure that adjoins a metallic surface of a substrate outside a perimeter of an electronic component attached to the metallic surface of the substrate and positioned adjacent to one or more sides of the electronic component, where excess solder adheres to the solder wetting structure.

公开(公告)号：US20220415732A1

公开(公告)日：2022-12-29

申请号：US17840971

申请日：2022-06-15

Applicant: Infineon Technologies AG

Inventor： Christoph Liebl ,  Stefan Schwab ,  Adrian Lis ,  Michael Ledutke ,  Lisa Aschenbrenner

IPC: H01L23/057 ,  H01L23/31 ,  H01L23/373

Abstract: A semiconductor module includes: a chip carrier having a first side and a second, opposite side; a semiconductor chip arranged on the first side of the chip carrier; an encapsulation body that encapsulates the semiconductor chip; and at least two external contacts made of a metal or an alloy and arranged next to each other, which are electrically and mechanically connected to the first side of the first chip carrier and protrude laterally out of the encapsulation body. At least one of the external contacts has at least one wing arranged within the encapsulation body and located opposite the other external contact. The wing includes one or more cutouts that are filled with the encapsulation material of the encapsulation body.

公开(公告)号：US12300643B2

公开(公告)日：2025-05-13

申请号：US17537822

申请日：2021-11-30

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Adrian Lis ,  Peter Scherl ,  Achim Althaus

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H05K1/11 ,  H05K1/18

Abstract: Described are solder stop features for electronic devices. An electronic device may include an electrically insulative substrate, a metallization on the electrically insulative substrate, a metal structure attached to a first main surface of the metallization via a solder joint, and a concavity formed in a sidewall of the metallization. The concavity is adjacent at least part of the solder joint and forms a solder stop. A first section of the metal structure is spaced apart from both the metallization and solder joint in a vertical direction that is perpendicular to the first main surface of the metallization. A linear dimension of the concavity in a horizontal direction that is coplanar with the metallization is at least twice the distance by which the first section of the metal structure is spaced apart from the first main surface of the metallization in the vertical direction. Additional solder stop embodiments are described.

公开(公告)号：US12113000B2

公开(公告)日：2024-10-08

申请号：US17540673

申请日：2021-12-02

Applicant: Infineon Technologies AG

Inventor： Ajay Poonjal Pai ,  Tino Karczewski ,  Adrian Lis

IPC: H01L23/495 ,  H01L23/31 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L23/49555 ,  H01L23/49517 ,  H01L25/072 ,  H01L25/18 ,  H01L23/3121

Abstract: A semiconductor package includes a first semiconductor die, an encapsulant body of electrically insulating mold compound that encapsulates the first semiconductor die, a plurality of power leads that protrude out of the encapsulant body and form power connections with the first semiconductor die, and a signal lead that protrudes out of the encapsulant body and forms a signal connection with the first semiconductor die, wherein the signal lead comprises a lead adapter retention feature that is configured to form an interlocked connection with a lead adapter that is fitted over an outer end of the signal lead.

公开(公告)号：US20240304527A1

公开(公告)日：2024-09-12

申请号：US18426415

申请日：2024-01-30

Applicant: Infineon Technologies AG

Inventor： Dominic Raithel ,  Adrian Lis ,  Thomas Schmid

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/538 ,  H01L25/07

CPC classification number: H01L23/49555 ,  H01L23/49534 ,  H01L23/49562 ,  H01L23/49811 ,  H01L23/5386 ,  H01L25/072

Abstract: A power module includes: a first substrate comprising a patterned first metallization; a second substrate comprising a patterned second metallization that faces the patterned first metallization; a first plurality of vertical power transistor dies having a drain pad attached to a first part of the patterned first metallization and a source pad electrically connected to a first part of the patterned second metallization; a second plurality of vertical power transistor dies having a drain pad attached to a second part of the patterned first metallization and a source pad electrically connected to a second part of the patterned second metallization; and a multi-level lead frame between the first substrate and the second substrate and attached to each of the first part of the patterned first metallization, the first part of the patterned second metallization, the second part of the patterned first metallization, and the second part of the patterned second metallization.