公开(公告)号：US12224222B2

公开(公告)日：2025-02-11

申请号：US17572858

申请日：2022-01-11

Applicant: Infineon Technologies AG

Inventor： Christian Neugirg ,  Adrian Lis ,  Peter Scherl ,  Ewald Guenther

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes: a first substrate having a first metallized side; a semiconductor die attached to the first metallized side of the first substrate at a first side of the die, a second side of the die opposite the first side being covered by a passivation, the passivation having a first opening that exposes at least part of a first pad at the second side of the die; a thermally and electrically conductive spacer attached to the part of the first pad that is exposed by the first opening in the passivation, the spacer at least partly overhanging the passivation along at least one side face of the semiconductor die; a second substrate having a first metallized side attached to the spacer at an opposite side of the spacer as the semiconductor die; and an encapsulant encapsulating the semiconductor die and the spacer. Additional spacer embodiments are described.

公开(公告)号：US20240413118A1

公开(公告)日：2024-12-12

申请号：US18332858

申请日：2023-06-12

Applicant: Infineon Technologies AG

Inventor： Peter Scherl ,  Adrian Lis

IPC: H01L23/00 ,  H05K1/02 ,  H05K1/18

Abstract: A power module is disclosed herein. In one embodiment, the power modules includes a solder repellent structure that adjoins a metallic surface of a substrate outside a perimeter of an electronic component attached to the metallic surface of the substrate and positioned adjacent to one or more sides of the electronic component, the solder repellent structure being configured to repel molten solder. In another embodiment, the power modules includes a solder wetting structure that adjoins a metallic surface of a substrate outside a perimeter of an electronic component attached to the metallic surface of the substrate and positioned adjacent to one or more sides of the electronic component, where excess solder adheres to the solder wetting structure.

公开(公告)号：US20190103342A1

公开(公告)日：2019-04-04

申请号：US15724920

申请日：2017-10-04

Applicant: Infineon Technologies AG

Inventor： Christian NEUGIRG ,  Peter Scherl

IPC: H01L23/495 ,  H01L21/48 ,  H01L25/18 ,  H01L25/00

Abstract: A semiconductor chip package may comprise a semiconductor chip disposed on a substrate. The semiconductor chip may have a first surface and a second surface. The first surface of the semiconductor chip may be connected to the substrate. The semiconductor chip package may comprise a leadframe that includes a first lead and a second lead. The first lead of the leadframe may be directly attached to the second surface of the semiconductor chip. The second lead of the leadframe may be directly attached to the substrate.

公开(公告)号：US20150124420A1

公开(公告)日：2015-05-07

申请号：US14071296

申请日：2013-11-04

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Peter Scherl ,  Magdalena Hoier ,  Hans-Joerg Timme

IPC: H05K1/11 ,  H05K3/36 ,  H05K1/14

CPC classification number: H05K1/11 ,  H01L24/45 ,  H01L24/46 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/45015 ,  H01L2224/45028 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45184 ,  H01L2224/4554 ,  H01L2224/48091 ,  H01L2224/48092 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48507 ,  H01L2224/48511 ,  H01L2224/85 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/181 ,  H05K1/111 ,  H05K1/14 ,  H05K3/32 ,  H05K3/36 ,  H05K3/4015 ,  H05K2201/04 ,  H05K2203/0285 ,  Y10T29/49126 ,  H01L2924/00 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00012 ,  H01L2224/48247 ,  H01L2224/43 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: An electronic device may comprise a semiconductor element and a wire bond connecting the semiconductor element to a substrate. Using a woven bonding wire may improve the mechanical and electrical properties of the wire bond. Furthermore, there may be a cost benefit. Woven bonding wires may be used in any electronic device, for example in power devices or integrated logic devices.

Abstract translation: 电子器件可以包括半导体元件和将半导体元件连接到衬底的引线键合。 使用编织的接合线可以改善引线接合的机械和电学性质。 此外，可能会有成本效益。 编织接合线可用于任何电子设备中，例如功率器件或集成逻辑器件中。

公开(公告)号：US20130075478A1

公开(公告)日：2013-03-28

申请号：US13626932

申请日：2012-09-26

Applicant: Infineon Technologies AG

Inventor： Peter Scherl ,  Frank Pueschner ,  Juergen Hoegerl

IPC: G06K19/067 ,  H05K13/00

CPC classification number: G06K19/025 ,  G06K19/07749

Abstract: In various embodiments, a cover structure for a personal identification document is provided. The cover structure may include a cover formed as a single layer; a chip module; the cover having a recess for completely receiving the chip module; and an antenna that is connected to the chip module.

Abstract translation: 在各种实施例中，提供了用于个人识别文件的盖结构。 盖结构可以包括形成为单层的盖; 芯片模块; 所述盖具有用于完全接收所述芯片模块的凹部; 以及连接到芯片模块的天线。

公开(公告)号：US12300643B2

公开(公告)日：2025-05-13

申请号：US17537822

申请日：2021-11-30

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Adrian Lis ,  Peter Scherl ,  Achim Althaus

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H05K1/11 ,  H05K1/18

Abstract: Described are solder stop features for electronic devices. An electronic device may include an electrically insulative substrate, a metallization on the electrically insulative substrate, a metal structure attached to a first main surface of the metallization via a solder joint, and a concavity formed in a sidewall of the metallization. The concavity is adjacent at least part of the solder joint and forms a solder stop. A first section of the metal structure is spaced apart from both the metallization and solder joint in a vertical direction that is perpendicular to the first main surface of the metallization. A linear dimension of the concavity in a horizontal direction that is coplanar with the metallization is at least twice the distance by which the first section of the metal structure is spaced apart from the first main surface of the metallization in the vertical direction. Additional solder stop embodiments are described.

公开(公告)号：US20230223312A1

公开(公告)日：2023-07-13

申请号：US17572858

申请日：2022-01-11

Applicant: Infineon Technologies AG

Inventor： Christian Neugirg ,  Adrian Lis ,  Peter Scherl ,  Ewald Guenther

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/367 ,  H01L23/49844 ,  H01L24/04 ,  H01L23/3171 ,  H01L23/3121 ,  H01L24/48 ,  H01L2224/48177 ,  H01L2224/04042

Abstract: A semiconductor package includes: a first substrate having a first metallized side; a semiconductor die attached to the first metallized side of the first substrate at a first side of the die, a second side of the die opposite the first side being covered by a passivation, the passivation having a first opening that exposes at least part of a first pad at the second side of the die; a thermally and electrically conductive spacer attached to the part of the first pad that is exposed by the first opening in the passivation, the spacer at least partly overhanging the passivation along at least one side face of the semiconductor die; a second substrate having a first metallized side attached to the spacer at an opposite side of the spacer as the semiconductor die; and an encapsulant encapsulating the semiconductor die and the spacer. Additional spacer embodiments are described.

公开(公告)号：US11652084B2

公开(公告)日：2023-05-16

申请号：US17078460

申请日：2020-10-23

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Gerald Ofner ,  Stephan Bradl ,  Stefan Miethaner ,  Alexander Heinrich ,  Horst Theuss ,  Peter Scherl

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/677 ,  H01L21/56 ,  H01L21/67 ,  H01L21/48 ,  H01L21/78

CPC classification number: H01L24/96 ,  H01L21/4825 ,  H01L21/4839 ,  H01L21/561 ,  H01L21/677 ,  H01L21/67011 ,  H01L21/67703 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/4952 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/97 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3107 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/0603 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/83005 ,  H01L2224/8384 ,  H01L2224/85005 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2224/8384 ,  H01L2924/00014 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2224/85 ,  H01L2224/291 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/00 ,  H01L2224/92247 ,  H01L2224/73265 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/00

Abstract: A method of forming a semiconductor package includes providing a panel, providing one or more metal layers on an upper surface of the panel, forming a die pad and bond pads from the one or more metal layers, the die pad being adjacent to and spaced apart from the bond pads, attaching a die to the die pad, forming electrical connections between the die and the bond pads, encapsulating the die and the electrical connections with an electrically insulating mold compound, removing portions of the panel, and exposing the die pad and the bond pads after encapsulating the die.

公开(公告)号：US09633303B2

公开(公告)日：2017-04-25

申请号：US14215229

申请日：2014-03-17

Applicant: Infineon Technologies AG

Inventor： Frank Pueschner ,  Juergen Hoegerl ,  Peter Scherl

IPC: G06K19/06 ,  G06K19/077

CPC classification number: G06K19/07756 ,  G06K19/07745 ,  G06K19/07749 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/181 ,  Y10T29/49018 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In various embodiments, a smart card module arrangement is provided. The smart card module arrangement includes a carrier, in which a depression is formed, a smart card module, which is arranged in the depression, and a smart card antenna. The smart card antenna can be coupled to the smart card module in a contactless manner.

公开(公告)号：US20140091450A1

公开(公告)日：2014-04-03

申请号：US14035579

申请日：2013-09-24

Applicant: Infineon Technologies AG

Inventor： Frank Pueschner ,  Juergen Hoegerl ,  Peter Scherl ,  Thomas Spoettl

IPC: H01L23/538

CPC classification number: H01L23/5388 ,  H01L23/49855 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/18161 ,  H01L2924/00012

Abstract: A semiconductor housing includes a front side with a semiconductor chip and a first metallization on a substrate, and a rear side with a second metallization. The rear side is situated opposite the front side of the semiconductor housing. The semiconductor housing further includes a first compensation layer applied on the front side of the semiconductor housing.

Abstract translation: 半导体外壳包括具有半导体芯片的前侧和在基板上的第一金属化，以及具有第二金属化的后侧。 后侧与半导体外壳的前侧相对。 半导体外壳还包括施加在半导体外壳的前侧的第一补偿层。