公开(公告)号：US12224222B2

公开(公告)日：2025-02-11

申请号：US17572858

申请日：2022-01-11

Applicant: Infineon Technologies AG

Inventor： Christian Neugirg ,  Adrian Lis ,  Peter Scherl ,  Ewald Guenther

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes: a first substrate having a first metallized side; a semiconductor die attached to the first metallized side of the first substrate at a first side of the die, a second side of the die opposite the first side being covered by a passivation, the passivation having a first opening that exposes at least part of a first pad at the second side of the die; a thermally and electrically conductive spacer attached to the part of the first pad that is exposed by the first opening in the passivation, the spacer at least partly overhanging the passivation along at least one side face of the semiconductor die; a second substrate having a first metallized side attached to the spacer at an opposite side of the spacer as the semiconductor die; and an encapsulant encapsulating the semiconductor die and the spacer. Additional spacer embodiments are described.

公开(公告)号：US20230223312A1

公开(公告)日：2023-07-13

申请号：US17572858

申请日：2022-01-11

Applicant: Infineon Technologies AG

Inventor： Christian Neugirg ,  Adrian Lis ,  Peter Scherl ,  Ewald Guenther

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/367 ,  H01L23/49844 ,  H01L24/04 ,  H01L23/3171 ,  H01L23/3121 ,  H01L24/48 ,  H01L2224/48177 ,  H01L2224/04042

Abstract: A semiconductor package includes: a first substrate having a first metallized side; a semiconductor die attached to the first metallized side of the first substrate at a first side of the die, a second side of the die opposite the first side being covered by a passivation, the passivation having a first opening that exposes at least part of a first pad at the second side of the die; a thermally and electrically conductive spacer attached to the part of the first pad that is exposed by the first opening in the passivation, the spacer at least partly overhanging the passivation along at least one side face of the semiconductor die; a second substrate having a first metallized side attached to the spacer at an opposite side of the spacer as the semiconductor die; and an encapsulant encapsulating the semiconductor die and the spacer. Additional spacer embodiments are described.

公开(公告)号：US20240047429A1

公开(公告)日：2024-02-08

申请号：US17881682

申请日：2022-08-05

Applicant: Infineon Technologies AG

Inventor： Adrian Lis ,  Ewald Guenther ,  Thomas Schmid

IPC: H01L25/07 ,  H01L23/00 ,  H01L23/373 ,  H01L21/66 ,  H01L25/00

CPC classification number: H01L25/072 ,  H01L24/48 ,  H01L23/3735 ,  H01L22/22 ,  H01L25/50 ,  H01L2224/48225

Abstract: A power module includes: a first substrate having a patterned first metallization; a second substrate vertically aligned with the first substrate and having a patterned second metallization that faces the patterned first metallization; first vertical power transistor dies having a drain pad attached to a first island of the patterned first metallization and a source pad electrically connected to a first island of the patterned second metallization via first spacers; and second vertical power transistor dies having a source pad electrically connected to the first island of the patterned first metallization via second spacers. A first subset of the second vertical power transistor dies has a drain pad attached to a second island of the patterned second metallization. A second subset of the second vertical power transistor dies has a drain pad attached to a third island of the patterned second metallization. A method of producing the module is described.