公开(公告)号：US20170125362A1

公开(公告)日：2017-05-04

申请号：US14928812

申请日：2015-10-30

Applicant: Infineon Technologies AG

Inventor： Xikun Zhang ,  Dejiang Chang ,  Bill Agar ,  Michael Lefevre ,  Alexander Komposch

IPC: H01L23/66 ,  H01L23/498 ,  H01L25/00 ,  H01L29/16 ,  H01L23/00 ,  H01L23/495 ,  H01L25/07

CPC classification number: H01L23/66 ,  H01L23/49503 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49844 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L25/072 ,  H01L25/50 ,  H01L29/16 ,  H01L2223/6644 ,  H01L2223/6672 ,  H01L2224/29111 ,  H01L2224/32245 ,  H01L2224/83136 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/13091 ,  H01L2924/19041

Abstract: A multi-die package is manufactured by attaching a first semiconductor die made of a first semiconductor material to a thermally conductive flange via a first die attach material, and attaching a second semiconductor die to the same thermally conductive flange as the first semiconductor die via a second die attach material. The second semiconductor die is made of a second semiconductor material different than the first semiconductor material. The first semiconductor die is held in place by the first die attach material during attachment of the second semiconductor die to the flange. Leads are attached to the thermally conductive flange or to an insulating member secured to the flange. The leads provide external electrical access to the first and second semiconductor dies.

公开(公告)号：US09589916B2

公开(公告)日：2017-03-07

申请号：US14618305

申请日：2015-02-10

Applicant: Infineon Technologies AG

Inventor： Marvin Marbell ,  E J Hashimoto ,  Bill Agar

IPC: H01L23/66 ,  H03H7/38 ,  H03F1/56 ,  H03F3/193

CPC classification number: H01L23/66 ,  H01L2224/49175 ,  H03F1/565 ,  H03F3/193 ,  H03F2200/534 ,  H03H7/38

Abstract: A packaged RF power transistor includes an RF input lead, a DC gate bias lead, an RF power transistor comprising gate, source and drain terminals, and an input match network. The input match network includes a primary inductor electrically connected to the RF input lead, a secondary inductor electrically connected to the gate terminal and to the DC gate bias lead, and a tuning capacitor electrically connected to the RF input lead and physically disconnected from the gate terminal. The input match network is configured to block DC voltages between the RF input lead and the gate terminal and to propagate AC voltages in a defined frequency range from the RF input lead to the gate terminal. The tuning capacitor is configured to adjust a capacitance of the input match network based upon a variation in DC voltage applied to the RF input lead.

Abstract translation: 封装的RF功率晶体管包括RF输入引线，DC栅极偏置引线，包括栅极，源极和漏极端子的RF功率晶体管以及输入匹配网络。 输入匹配网络包括电连接到RF输入引线的初级电感器，电连接到栅极端子和DC栅极偏置引线的次级电感器，以及电连接到RF输入引线并与栅极物理断开的调谐电容器 终奌站。 输入匹配网络被配置为阻止RF输入引线和栅极端子之间的直流电压，并且将从RF输入引线到栅极端子的规定频率范围内的交流电压传播。 调谐电容器被配置为基于施加到RF输入引线的DC电压的变化来调整输入匹配网络的电容。

公开(公告)号：US20180254253A1

公开(公告)日：2018-09-06

申请号：US15973276

申请日：2018-05-07

Applicant: Infineon Technologies AG

Inventor： Xikun Zhang ,  Dejiang Chang ,  Bill Agar ,  Michael Lefevre ,  Alexander Komposch

IPC: H01L23/66 ,  H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L25/07 ,  H01L25/00 ,  H01L29/16

CPC classification number: H01L23/66 ,  H01L23/49503 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49844 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L25/072 ,  H01L25/50 ,  H01L29/16 ,  H01L2223/6644 ,  H01L2223/6672 ,  H01L2224/29111 ,  H01L2224/32245 ,  H01L2224/83136 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/13091 ,  H01L2924/19041

Abstract: A multi-die package includes a thermally conductive flange, a first semiconductor die made of a first semiconductor material attached to the thermally conductive flange via a first die attach material, a second semiconductor die attached to the same thermally conductive flange as the first semiconductor die via a second die attach material, and leads attached to the thermally conductive flange or to an insulating member secured to the flange. The leads are configured to provide external electrical access to the first and second semiconductor dies. The second semiconductor die is made of a second semiconductor material different than the first semiconductor material. Additional multi-die package embodiments are described.

公开(公告)号：US10332847B2

公开(公告)日：2019-06-25

申请号：US15610805

申请日：2017-06-01

Applicant: Infineon Technologies AG

Inventor： Yang Liu ,  Xikun Zhang ,  Bill Agar

IPC: H01L23/495 ,  H01L23/047 ,  H01L23/66 ,  H01L23/58 ,  H01L23/00 ,  H01L25/07 ,  H01P3/08 ,  H03F3/193

Abstract: A semiconductor package includes a metal flange having a lower surface and an upper surface opposite the lower surface. An electrically insulating window frame is disposed on the upper surface of the flange. The electrically insulating window frame forms a ring around a periphery of the metal flange so as to expose the upper surface of the metal flange in a central die attach region. A first electrically conductive lead is disposed on the electrically insulating window frame and extends away from a first side of the metal flange. A second electrically conductive lead is disposed on the electrically insulating window frame and extends away from a second side of the metal flange, the second side being opposite the first side. A first harmonic filtering feature is formed on a portion of the electrically insulating window frame and is electrically connected to the first electrically conductive lead.

公开(公告)号：US20180350758A1

公开(公告)日：2018-12-06

申请号：US15610805

申请日：2017-06-01

Applicant: Infineon Technologies AG

Inventor： Yang Liu ,  Xikun Zhang ,  Bill Agar

IPC: H01L23/66 ,  H01L23/495 ,  H01L23/58 ,  H01P3/08 ,  H03F3/193 ,  H01L25/07

CPC classification number: H01L23/66 ,  H01L23/047 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/585 ,  H01L24/48 ,  H01L25/072 ,  H01L2223/6611 ,  H01L2223/6627 ,  H01L2223/6644 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48175 ,  H01L2224/48195 ,  H01L2924/13055 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/19032 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01P3/081 ,  H03F3/193 ,  H03F2200/165 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/451

Abstract: A semiconductor package includes a metal flange having a lower surface and an upper surface opposite the lower surface. An electrically insulating window frame is disposed on the upper surface of the flange. The electrically insulating window frame forms a ring around a periphery of the metal flange so as to expose the upper surface of the metal flange in a central die attach region. A first electrically conductive lead is disposed on the electrically insulating window frame and extends away from a first side of the metal flange. A second electrically conductive lead is disposed on the electrically insulating window frame and extends away from a second side of the metal flange, the second side being opposite the first side. A first harmonic filtering feature is formed on a portion of the electrically insulating window frame and is electrically connected to the first electrically conductive lead.

公开(公告)号：US09997476B2

公开(公告)日：2018-06-12

申请号：US14928812

申请日：2015-10-30

Applicant: Infineon Technologies AG

Inventor： Xikun Zhang ,  Dejiang Chang ,  Bill Agar ,  Michael Lefevre ,  Alexander Komposch

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/498 ,  H01L23/495 ,  H01L25/07 ,  H01L29/16 ,  H01L25/00

CPC classification number: H01L23/66 ,  H01L23/49503 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49844 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L25/072 ,  H01L25/50 ,  H01L29/16 ,  H01L2223/6644 ,  H01L2223/6672 ,  H01L2224/29111 ,  H01L2224/32245 ,  H01L2224/83136 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/13091 ,  H01L2924/19041

Abstract: A multi-die package is manufactured by attaching a first semiconductor die made of a first semiconductor material to a thermally conductive flange via a first die attach material, and attaching a second semiconductor die to the same thermally conductive flange as the first semiconductor die via a second die attach material. The second semiconductor die is made of a second semiconductor material different than the first semiconductor material. The first semiconductor die is held in place by the first die attach material during attachment of the second semiconductor die to the flange. Leads are attached to the thermally conductive flange or to an insulating member secured to the flange. The leads provide external electrical access to the first and second semiconductor dies.

公开(公告)号：US20160233849A1

公开(公告)日：2016-08-11

申请号：US14618305

申请日：2015-02-10

Applicant: Infineon Technologies AG

Inventor： Marvin Marbell ,  EJ Hashimoto ,  Bill Agar

IPC: H03H11/28

CPC classification number: H01L23/66 ,  H01L2224/49175 ,  H03F1/565 ,  H03F3/193 ,  H03F2200/534 ,  H03H7/38

Abstract: A packaged RF power transistor includes an RF input lead, a DC gate bias lead, an RF power transistor comprising gate, source and drain terminals, and an input match network. The input match network includes a primary inductor electrically connected to the RF input lead, a secondary inductor electrically connected to the gate terminal and to the DC gate bias lead, and a tuning capacitor electrically connected to the RF input lead and physically disconnected from the gate terminal. The input match network is configured to block DC voltages between the RF input lead and the gate terminal and to propagate AC voltages in a defined frequency range from the RF input lead to the gate terminal. The tuning capacitor is configured to adjust a capacitance of the input match network based upon a variation in DC voltage applied to the RF input lead.

Abstract translation: 封装的RF功率晶体管包括RF输入引线，DC栅极偏置引线，包括栅极，源极和漏极端子的RF功率晶体管以及输入匹配网络。 输入匹配网络包括电连接到RF输入引线的初级电感器，电连接到栅极端子和DC栅极偏置引线的次级电感器，以及电连接到RF输入引线并与栅极物理断开的调谐电容器 终奌站。 输入匹配网络被配置为阻止RF输入引线和栅极端子之间的直流电压，并且将从RF输入引线到栅极端子的规定频率范围内的交流电压传播。 调谐电容器被配置为基于施加到RF输入引线的DC电压的变化来调整输入匹配网络的电容。