公开(公告)号：US11075185B2

公开(公告)日：2021-07-27

申请号：US16575006

申请日：2019-09-18

Applicant: Infineon Technologies AG

Inventor： Chii Shang Hong ,  Ivan Nikitin ,  Wei Han Koo ,  Chiew Li Tai

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/367 ,  H01L23/31

Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip including a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and a support extending between the first segment and the second segment. The package further includes an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from a planar surface of the encapsulant. A lower surface of the second segment is flush against the upper surface of the semiconductor die and conductively connected to the first bond pad.

公开(公告)号：US10971436B2

公开(公告)日：2021-04-06

申请号：US16440037

申请日：2019-06-13

Applicant: Infineon Technologies AG

Inventor： Thomas Stoek ,  Chii Shang Hong ,  Chiew Li Tai ,  Edmund Sales Cabatbat

IPC: H01L23/495 ,  H01L23/00

Abstract: An example multi-branch terminal for an integrated circuit (IC) package is described herein. An example multi-branch terminal of an integrated circuit (IC), may include a first branch that may include an active bonding with a chip of the IC, wherein the active bonding may include a wire bonded to the chip of the IC; and a second branch that may include a passive bonding with the chip of the IC, wherein the passive bonding may include a capacitor bonded to the second branch and a first terminal of the IC.

公开(公告)号：US10354943B1

公开(公告)日：2019-07-16

申请号：US16033756

申请日：2018-07-12

Applicant: Infineon Technologies AG

Inventor： Thomas Stoek ,  Chii Shang Hong ,  Chiew Li Tai ,  Edmund Sales Cabatbat

IPC: H01L23/495 ,  H01L23/00

Abstract: An example multi-branch terminal for an integrated circuit (IC) package is described herein. An example multi-branch terminal of an integrated circuit (IC), may include a first branch that may include an active bonding with a chip of the IC, wherein the active bonding may include a wire bonded to the chip of the IC; and a second branch that may include a passive bonding with the chip of the IC, wherein the passive bonding may include a capacitor bonded to the second branch and a first terminal of the IC.

公开(公告)号：US10083899B2

公开(公告)日：2018-09-25

申请号：US15412108

申请日：2017-01-23

Applicant: Infineon Technologies AG

Inventor： Mohd Kahar Bajuri ,  Edmund Sales Cabatbat ,  Gaylord Evangelista Cruz ,  Amirul Afiq Hud ,  Teck Sim Lee ,  Norbert Joson Santos ,  Chiew Li Tai ,  Chin Wei Yang

IPC: H01L23/40 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49568 ,  H01L21/4853 ,  H01L21/4882 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/4334 ,  H01L23/49541 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A method of forming a semiconductor device package includes providing a lead frame having a peripheral structure and a heat slug having an upper and lower surface, the heat slug being attached to the peripheral structure. A semiconductor die is attached to the heat slug. The semiconductor die is encapsulated with a molding compound while the heat slug is attached to the peripheral structure. The heat slug is completely devoid of fasteners before the encapsulating.

公开(公告)号：US20200350238A1

公开(公告)日：2020-11-05

申请号：US16402486

申请日：2019-05-03

Applicant: Infineon Technologies AG

Inventor： Chii Shang Hong ,  Wei Han Koo ,  Chiew Li Tai

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip, having a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and one or more supports connected between the first segment and the second segment, and an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from an upper surface of the encapsulant. A lower surface of the second segment is flush against the first bond pad.

公开(公告)号：US10431526B2

公开(公告)日：2019-10-01

申请号：US15727725

申请日：2017-10-09

Applicant: Infineon Technologies AG

Inventor： Kar Meng Ho ,  Chiew Li Tai ,  Jia Yi Wong ,  Sanjay Kumar Murugan

IPC: H01L23/492 ,  H01L21/48 ,  H01L23/14 ,  H01L23/047 ,  H01L23/31 ,  H01L23/367

Abstract: A metal heat slug having an upper and lower surface is provided. First and second electrically conductive leads are provided. First and second electrically insulating fastening mechanisms are provided. The first and second fastening mechanisms are adhered to the upper surface of the heat slug in an outer peripheral region of the heat slug such that the first and second leads are vertically separated from and electrically insulated from the heat slug. The central die attach region is exposed from the first and second fastening mechanisms after adhering the first and second fastening mechanisms to the upper surface of the heat slug.

公开(公告)号：US20190109070A1

公开(公告)日：2019-04-11

申请号：US15727725

申请日：2017-10-09

Applicant: Infineon Technologies AG

Inventor： Kar Meng Ho ,  Chiew Li Tai ,  Jia Yi Wong ,  Sanjay Kumar Murugan

IPC: H01L23/492 ,  H01L23/14 ,  H01L21/48

CPC classification number: H01L23/492 ,  H01L21/481 ,  H01L21/4814 ,  H01L23/047 ,  H01L23/14 ,  H01L23/315 ,  H01L23/367 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/49111 ,  H01L2924/00014

Abstract: A metal heat slug having an upper and lower surface is provided. First and second electrically conductive leads are provided. First and second electrically insulating fastening mechanisms are provided. The first and second fastening mechanisms are adhered to the upper surface of the heat slug in an outer peripheral region of the heat slug such that the first and second leads are vertically separated from and electrically insulated from the heat slug. The central die attach region is exposed from the first and second fastening mechanisms after adhering the first and second fastening mechanisms to the upper surface of the heat slug.

公开(公告)号：US10978380B2

公开(公告)日：2021-04-13

申请号：US16402486

申请日：2019-05-03

Applicant: Infineon Technologies AG

Inventor： Chii Shang Hong ,  Wei Han Koo ,  Chiew Li Tai

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip, having a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and one or more supports connected between the first segment and the second segment, and an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from an upper surface of the encapsulant. A lower surface of the second segment is flush against the first bond pad.

公开(公告)号：US20200350272A1

公开(公告)日：2020-11-05

申请号：US16575006

申请日：2019-09-18

Applicant: Infineon Technologies AG

Inventor： Chii Shang Hong ,  Ivan Nikitin ,  Wei Han Koo ,  Chiew Li Tai

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/56

Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip including a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and a support extending between the first segment and the second segment. The package further includes an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from a planar surface of the encapsulant. A lower surface of the second segment is flush against the upper surface of the semiconductor die and conductively connected to the first bond pad.

公开(公告)号：US20180211907A1

公开(公告)日：2018-07-26

申请号：US15412108

申请日：2017-01-23

Applicant: Infineon Technologies AG

Inventor： Mohd Kahar Bajuri ,  Edmund Sales Cabatbat ,  Gaylord Evangelista Cruz ,  Amirul Afiq Hud ,  Teck Sim Lee ,  Norbert Joson Santos ,  Chiew Li Tai ,  Chin Wei Yang

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L21/4853 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/4334 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A method of forming a semiconductor device package includes providing a lead frame having a peripheral structure and a heat slug having an upper and lower surface, the heat slug being attached to the peripheral structure. A semiconductor die is attached to the heat slug. The semiconductor die is encapsulated with a molding compound while the heat slug is attached to the peripheral structure. The heat slug is completely devoid of fasteners before the encapsulating.