公开(公告)号：US10396018B2

公开(公告)日：2019-08-27

申请号：US15822745

申请日：2017-11-27

Applicant: Infineon Technologies AG

Inventor： Chau Fatt Chiang ,  Chan Lam Cha ,  Wei Han Koo ,  Andreas Kucher ,  Theng Chao Long

IPC: H01L23/52 ,  H01L21/60 ,  H01L23/495 ,  H03K17/687 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H02M1/088 ,  H02P27/04

Abstract: A semiconductor package includes a plurality of half bridge assemblies each including a metal lead, a first power transistor die attached to a first side of the metal lead, and a second power transistor die disposed under the first power transistor die and attached to a second side of the metal lead opposite the first side. Each metal lead has a notch which exposes one or more bond pads at a side of the second power transistor die attached to the metal lead. The semiconductor package also includes a controller die configured to control the power transistor dies. Each power transistor die, each metal lead and the controller die are embedded in a mold compound. Bond wire connections are provided between the controller die and the one or more bond pads at the side of each second power transistor die exposed by the notch in the corresponding metal lead.

公开(公告)号：US11075185B2

公开(公告)日：2021-07-27

申请号：US16575006

申请日：2019-09-18

Applicant: Infineon Technologies AG

Inventor： Chii Shang Hong ,  Ivan Nikitin ,  Wei Han Koo ,  Chiew Li Tai

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/367 ,  H01L23/31

Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip including a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and a support extending between the first segment and the second segment. The package further includes an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from a planar surface of the encapsulant. A lower surface of the second segment is flush against the upper surface of the semiconductor die and conductively connected to the first bond pad.

公开(公告)号：US10978380B2

公开(公告)日：2021-04-13

申请号：US16402486

申请日：2019-05-03

Applicant: Infineon Technologies AG

Inventor： Chii Shang Hong ,  Wei Han Koo ,  Chiew Li Tai

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip, having a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and one or more supports connected between the first segment and the second segment, and an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from an upper surface of the encapsulant. A lower surface of the second segment is flush against the first bond pad.

公开(公告)号：US20200350272A1

公开(公告)日：2020-11-05

申请号：US16575006

申请日：2019-09-18

Applicant: Infineon Technologies AG

Inventor： Chii Shang Hong ,  Ivan Nikitin ,  Wei Han Koo ,  Chiew Li Tai

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/56

Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip including a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and a support extending between the first segment and the second segment. The package further includes an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from a planar surface of the encapsulant. A lower surface of the second segment is flush against the upper surface of the semiconductor die and conductively connected to the first bond pad.

公开(公告)号：US10727151B2

公开(公告)日：2020-07-28

申请号：US15605091

申请日：2017-05-25

Applicant: Infineon Technologies AG

Inventor： Liu Chen ,  Teck Sim Lee ,  Jia Yi Wong ,  Wei Han Koo ,  Thomas Stoeck ,  Gilles Delarozee

IPC: H01L23/367 ,  H01L23/492 ,  H01L23/495 ,  H01L21/56 ,  H01L23/433 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498 ,  H01L23/373

Abstract: A semiconductor chip package includes an electrically conducting carrier and a semiconductor chip disposed over the electrically conducting carrier. The semiconductor chip has a first surface facing the electrically conducting carrier and a second surface opposite the first surface. A metal plate has a first surface mechanically connected to the second surface of the semiconductor chip and a second surface opposite the first surface of the metal plate. The metal plate completely overlaps the second surface of the semiconductor chip. The second surface of the metal plate is at least partially exposed at a periphery of the semiconductor chip package.

公开(公告)号：US20200350238A1

公开(公告)日：2020-11-05

申请号：US16402486

申请日：2019-05-03

Applicant: Infineon Technologies AG

Inventor： Chii Shang Hong ,  Wei Han Koo ,  Chiew Li Tai

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip, having a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and one or more supports connected between the first segment and the second segment, and an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from an upper surface of the encapsulant. A lower surface of the second segment is flush against the first bond pad.

公开(公告)号：US20190164873A1

公开(公告)日：2019-05-30

申请号：US15822745

申请日：2017-11-27

Applicant: Infineon Technologies AG

Inventor： Chau Fatt Chiang ,  Chan Lam Cha ,  Wei Han Koo ,  Andreas Kucher ,  Theng Chao Long

IPC: H01L23/495 ,  H03K17/687 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49575 ,  H01L21/4803 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49568 ,  H02M1/088 ,  H02P27/04 ,  H03K17/6871

Abstract: A semiconductor package includes a plurality of half bridge assemblies each including a metal lead, a first power transistor die attached to a first side of the metal lead, and a second power transistor die disposed under the first power transistor die and attached to a second side of the metal lead opposite the first side. Each metal lead has a notch which exposes one or more bond pads at a side of the second power transistor die attached to the metal lead. The semiconductor package also includes a controller die configured to control the power transistor dies. Each power transistor die, each metal lead and the controller die are embedded in a mold compound. Bond wire connections are provided between the controller die and the one or more bond pads at the side of each second power transistor die exposed by the notch in the corresponding metal lead.

公开(公告)号：US20180342438A1

公开(公告)日：2018-11-29

申请号：US15605091

申请日：2017-05-25

Applicant: Infineon Technologies AG

Inventor： Liu Chen ,  Teck Sim Lee ,  Jia Yi Wong ,  Wei Han Koo ,  Thomas Stoek ,  Gilles Delarozee

IPC: H01L23/367 ,  H01L23/492 ,  H01L23/495 ,  H01L21/56

Abstract: A semiconductor chip package includes an electrically conducting carrier and a semiconductor chip disposed over the electrically conducting carrier. The semiconductor chip has a first surface facing the electrically conducting carrier and a second surface opposite the first surface. A metal plate has a first surface mechanically connected to the second surface of the semiconductor chip and a second surface opposite the first surface of the metal plate. The metal plate completely overlaps the second surface of the semiconductor chip. The second surface of the metal plate is at least partially exposed at a periphery of the semiconductor chip package.