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    Transistor package with three-terminal clip
    1.
    发明授权
    Transistor package with three-terminal clip 有权

    公开(公告)号：US10290567B2

    公开(公告)日：2019-05-14

    申请号：US15694086

    申请日：2017-09-01

    Applicant: Infineon Technologies AG

    Inventor： Rainald Sander ,  Liu Chen ,  Teck Sim Lee

    IPC: H01L23/49 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31

    Abstract: A package which comprises an electrically conductive chip carrier, a first chip comprising a first connection terminal, a second connection terminal located on the chip carrier and a control terminal, a second chip comprising a first connection terminal, a second connection terminal located on the chip carrier and a control terminal, wherein the first chip and the second chip are connected to form a half bridge having inlet terminals and an outlet terminal, and a clip having three connection sections connecting the second connection terminal of the first chip with the first connection terminal of the second chip and with the outlet terminal of the half bridge.

    Multi-Chip Package
    5.
    发明申请
    Multi-Chip Package 有权

    公开(公告)号：US20210074614A1

    公开(公告)日：2021-03-11

    申请号：US17012198

    申请日：2020-09-04

    Applicant: Infineon Technologies AG

    Inventor： Ralf Otremba ,  Teck Sim Lee ,  Lee Shuang Wang ,  Mohd Hasrul Zulkifli

    IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

    Abstract: A package includes a package body with a package top side, package footprint side and package sidewalls extending from the package footprint side to the package top side; power semiconductor chips electrically connected in parallel and each having first and second load terminals and being configured to block a blocking voltage and conduct a chip load current between the load terminals; a lead frame structure configured to electrically and mechanically couple the package to a carrier with the package footprint side facing the carrier, the lead frame structure including first outside terminals extending out of the package body for interfacing with the carrier. Each first load terminal is electrically connected, at least by one package body internal connection member, to at least two of the first outside terminals. A horizontally extending conduction layer at the package top side or footprint side is electrically connected with each second load terminal.

    Method of electrically isolating shared leads of a lead frame strip
    6.
    发明授权
    Method of electrically isolating shared leads of a lead frame strip 有权
    电隔离引线框带的共用引线的方法

    公开(公告)号：US09324642B2

    公开(公告)日：2016-04-26

    申请号：US14077582

    申请日：2013-11-12

    Applicant: Infineon Technologies AG

    Inventor： Frank Püschner ,  Bernhard Schätzler ,  Teck Sim Lee ,  Franz Gabler ,  Pei Pei Kong ,  Boon Huat Lim

    IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L21/66 ,  H01L21/56 ,  H01L23/31

    CPC classification number: H01L23/49541 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/561 ,  H01L22/14 ,  H01L23/3107 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/97 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

    Abstract: A lead frame strip includes a plurality of connected unit lead frames, each unit lead frame having a die paddle and a plurality of leads connected to a periphery of the unit lead frame. A semiconductor die is attached to the die paddles. A molding compound covers the unit lead frames, including the semiconductor dies. Prior to testing or other processing of the lead frame strip, a gap is etched into a region of the leads which are shared by adjacent ones of the unit lead frames. The gap extends at least mostly through the shared leads. A partial cut is made in the molding compound around the periphery of the unit lead frames prior to the subsequent processing, including below the gap in the shared leads, to electrically isolate the leads of the unit lead frames.

    Abstract translation: 引线框架条包括多个连接的单元引线框架，每个单元引线框架具有管芯焊盘和连接到单元引线框架的外围的多个引线。 将半导体管芯附接到管芯片。 模制化合物覆盖包括半导体管芯的单元引线框架。 在引线框架条的测试或其它处理之前，间隙被蚀刻到由相邻单元引线框架共享的引线的区域中。 差距至少主要通过共享潜在客户。 在随后的处理之前，在包括在共享引线之间的间隙的下方的单元引线框的周围的模塑料中部分地切割，以使单元引线框架的引线电隔离。

    Multi-chip package
    8.
    发明授权
    Multi-chip package 有权

    公开(公告)号：US11355424B2

    公开(公告)日：2022-06-07

    申请号：US17012198

    申请日：2020-09-04

    Applicant: Infineon Technologies AG

    Inventor： Ralf Otremba ,  Teck Sim Lee ,  Lee Shuang Wang ,  Mohd Hasrul Zulkifli

    IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

    Abstract: A package includes a package body with a package top side, package footprint side and package sidewalls extending from the package footprint side to the package top side; power semiconductor chips electrically connected in parallel and each having first and second load terminals and being configured to block a blocking voltage and conduct a chip load current between the load terminals; a lead frame structure configured to electrically and mechanically couple the package to a carrier with the package footprint side facing the carrier, the lead frame structure including first outside terminals extending out of the package body for interfacing with the carrier. Each first load terminal is electrically connected, at least by one package body internal connection member, to at least two of the first outside terminals. A horizontally extending conduction layer at the package top side or footprint side is electrically connected with each second load terminal.

    Semiconductor package for multiphase circuitry device
    9.
    发明授权
    Semiconductor package for multiphase circuitry device 有权

    公开(公告)号：US10147703B2

    公开(公告)日：2018-12-04

    申请号：US15469112

    申请日：2017-03-24

    Applicant: Infineon Technologies AG

    Inventor： Stefan Macheiner ,  Amirul Afiq Hud ,  Teck Sim Lee ,  Thomas Stoek ,  Lee Shuang Wang ,  Chooi Mei Chong ,  Wei Hing Tan

    IPC: H01L23/52 ,  H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L23/057 ,  H01L25/00 ,  H01L29/78

    Abstract: In some examples, a device includes a power supply element and a reference voltage element, wherein the reference voltage element is electrically isolated from the power supply element. The device further includes a high-side semiconductor die including at least two high-side transistors, wherein each high-side transistor of the at least two high-side transistors is electrically connected to the power supply element. The device also includes a low-side semiconductor die including at least two low-side transistors, wherein each low-side transistor of the at least two low-side transistors is electrically connected to the reference voltage element. The device includes at least two switching elements, wherein each switching element of the at least two switching elements is electrically connected to a respective high-side transistor of the at least two high-side transistors and to a respective low-side transistor of the at least two low-side transistors.

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