公开(公告)号：US08754673B1

公开(公告)日：2014-06-17

申请号：US13936900

申请日：2013-07-08

Applicant: Integrated Device Technology, Inc.

Inventor： Wei Wang ,  Yumin Zhang

IPC: H03K5/22

CPC classification number: H03K5/2481

Abstract: An integrated circuit device includes a reference voltage generator, which is configured to generate an adaptive reference voltage (Vref) that varies inversely relative to changes in magnitude of a data signal (DATA) received at an input thereof. This reference voltage generator includes a totem pole arrangement of at least two variable impedance elements having control terminals capacitively coupled (by respective capacitors) to the input. A current mirror is electrically coupled to the totem pole arrangement of at least two variable impedance elements. A comparator is also included. The comparator has a first input terminal that receives the adaptive reference voltage and a second input terminal that receives the data signal.

Abstract translation: 集成电路装置包括参考电压发生器，其被配置为产生相对于在其输入处接收的数据信号（DATA）的幅度变化而相反变化的自适应参考电压（Vref）。 该参考电压发生器包括具有至少两个可变阻抗元件的图腾柱布置，该可变阻抗元件具有与输入电容耦合（通过相应的电容器）的控制端。 电流镜电耦合到至少两个可变阻抗元件的图腾柱布置。 还包括一个比较器。 比较器具有接收自适应参考电压的第一输入端子和接收数据信号的第二输入端子。

公开(公告)号：US09589626B1

公开(公告)日：2017-03-07

申请号：US14993271

申请日：2016-01-12

Applicant: Integrated Device Technology, Inc.

Inventor： HaiQi Liu ,  Yue Yu ,  Yumin Zhang ,  Yi Xie

IPC: G11C7/10 ,  G11C11/4074 ,  G11C11/4093 ,  G11C7/22

CPC classification number: G11C11/4074 ,  G11C5/04 ,  G11C5/148 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C11/4093

Abstract: An apparatus having a first circuit and a second circuit. The first circuit may be configured to buffer an input signal received as a single-ended signal from a data bus connected between a memory channel and a memory controller. The second circuit may be configured to condition the input signal relative to a reference voltage to generate a differential signal. The reference voltage may be isolated from the second circuit in response to a transition from a power down condition to a power on condition.

Abstract translation: 一种具有第一电路和第二电路的装置。 第一电路可以被配置为缓冲从连接在存储器通道和存储器控制器之间的数据总线作为单端信号接收的输入信号。 第二电路可以被配置为相对于参考电压调节输入信号以产生差分信号。 响应于从断电状态到电源接通状态的转变，参考电压可以与第二电路隔离。