公开(公告)号：US20220091895A1

公开(公告)日：2022-03-24

申请号：US17541016

申请日：2021-12-02

Applicant: Intel Corporation

Inventor： Niranjan Hasabnis ,  Justin Gottschlich ,  Jesmin Jahan Tithi ,  Anand Venkat

IPC: G06F9/50 ,  G06F9/30 ,  G06F9/455 ,  G06F9/38

Abstract: Methods, apparatus, systems, and articles of manufacture to determine execution cost are disclosed. An example apparatus includes memory; instructions included in the apparatus; and processor circuitry to execute the instruction to: cause a plurality of instructions corresponding to a mnemonic to be executed; determine an average execution cost of the plurality of instructions; determine a standard deviation of execution costs of the plurality of instructions; and generate a mapping table including an entry, the entry including the mnemonic in association with the average and the standard deviation.

公开(公告)号：US11733981B2

公开(公告)日：2023-08-22

申请号：US17103477

申请日：2020-11-24

Applicant: Intel Corporation

Inventor： Anand Venkat ,  Justin Gottschlich ,  Shengtian Zhou ,  Vasileios Porpodas

IPC: G06F9/44 ,  G06F8/41 ,  G06F16/22 ,  G06F8/75 ,  G06F8/77

CPC classification number: G06F8/443 ,  G06F8/75 ,  G06F8/77 ,  G06F16/2255

Abstract: An example apparatus comprises a transformation generator to generate a population of code variants corresponding to an input code, the population of code variants to include transformation sequences of the input code, a dependence analyzer to analyze the population of code variants for dependence vectors, a profile controller to profile the population of code variants to determine performance metrics of hardware during an execution of respective ones of the transformation sequences, and a hash code generator to generate hash codes for storing in a database, the hash codes (a) corresponding to a combination of the dependence vectors and respective performance metrics and (b) mapped to respective transformation sequences.

公开(公告)号：US20220121430A1

公开(公告)日：2022-04-21

申请号：US17561417

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Anand Venkat ,  Justin Gottschlich ,  Niranjan Hasabnis

IPC: G06F8/41 ,  G06N5/00

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that perform machine learning-guided compiler optimizations for register-based hardware architectures. Examples disclosed herein include a non-transitory computer readable medium comprising instructions that, when executed, cause a machine to at least select a register-based compiler transformation to apply to source code at a current position in a search tree, determine whether the search tree is in need of pruning based on an output of a query to a machine learning (ML) model, in response to determining the search tree is in need of pruning, prune the search tree at the current position, in response to applying the selected register-based compiler transformation to the source code, generate a code variant, calculate a score associated with the source code at the current position in the search tree, and update parameters of the machine learning (ML) model to include the calculated score.

公开(公告)号：US11954466B2

公开(公告)日：2024-04-09

申请号：US17561417

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Anand Venkat ,  Justin Gottschlich ,  Niranjan Hasabnis

IPC: G06F9/44 ,  G06F8/41 ,  G06N5/01

CPC classification number: G06F8/443 ,  G06N5/01

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that perform machine learning-guided compiler optimizations for register-based hardware architectures. Examples disclosed herein include a non-transitory computer readable medium comprising instructions that, when executed, cause a machine to at least select a register-based compiler transformation to apply to source code at a current position in a search tree, determine whether the search tree is in need of pruning based on an output of a query to a machine learning (ML) model, in response to determining the search tree is in need of pruning, prune the search tree at the current position, in response to applying the selected register-based compiler transformation to the source code, generate a code variant, calculate a score associated with the source code at the current position in the search tree, and update parameters of the machine learning (ML) model to include the calculated score.

公开(公告)号：US20210103434A1

公开(公告)日：2021-04-08

申请号：US17103477

申请日：2020-11-24

Applicant: Intel Corporation

Inventor： Anand Venkat ,  Justin Gottschlich ,  Shengtian Zhou ,  Vasileios Porpodas

IPC: G06F8/41 ,  G06F8/77 ,  G06F8/75 ,  G06F16/22

Abstract: An example apparatus comprises a transformation generator to generate a population of code variants corresponding to an input code, the population of code variants to include transformation sequences of the input code, a dependence analyzer to analyze the population of code variants for dependence vectors, a profile controller to profile the population of code variants to determine performance metrics of hardware during an execution of respective ones of the transformation sequences, and a hash code generator to generate hash codes for storing in a database, the hash codes (a) corresponding to a combination of the dependence vectors and respective performance metrics and (b) mapped to respective transformation sequences.