METHODS AND APPARATUS TO TRAIN MODELS FOR PROGRAM SYNTHESIS

    公开(公告)号:US20220108182A1

    公开(公告)日:2022-04-07

    申请号:US17551170

    申请日:2021-12-14

    Abstract: Methods and apparatus to train models for program synthesis are disclosed. A disclosed example apparatus includes at least one memory, instructions, and processor circuitry. The processor circuitry is to execute the instructions to sample pairs of programs, the pairs of programs including first programs and second programs, the first programs including natural language descriptions and second programs, calculate program similarity scores corresponding to the pairs of programs, and train a model based on entries corresponding to ones of the pairs of programs, at least one of the entries including a corresponding one of the natural language descriptions with a paired one of the second programs, and a corresponding one of the program similarity scores.

    METHODS AND APPARATUS TO DETECT SIDE-CHANNEL ATTACKS

    公开(公告)号:US20220019666A1

    公开(公告)日:2022-01-20

    申请号:US17385589

    申请日:2021-07-26

    Abstract: Methods, apparatus, systems and articles of manufacture to identify a side-channel attack are disclosed. Example instructions cause one or more processors to generate an event vector based on one or more counts corresponding to tasks performed by a central processing unit; determine distances between the event vector and weight vectors of neurons in a self-organizing map; select a neuron of the neurons that results based on a determined distance; identify neurons that neighbor the selected neuron; and update at least one of a weight vector of the selected neuron or weight vectors of the neighboring neurons based on the determined distance of the selected neuron.

    Methods and apparatus to detect side-channel attacks

    公开(公告)号:US11074344B2

    公开(公告)日:2021-07-27

    申请号:US16226137

    申请日:2018-12-19

    Abstract: Methods, apparatus, systems and articles of manufacture to identify a side-channel attack are disclosed. An example apparatus includes a vector-to-neuron processor to map an event vector to a neuron of a trained self-organizing map; a buffer processor to identify a task pair based on the neuron and an adjacent neuron of the neuron; a buffer to store data corresponding to the identified task pair; an attack identifier to, when information stored in the buffer corresponds to more than a threshold number of task pairs corresponding to the identified task pair, identify a malware attack; and a mitigation technique selector to select a technique for mitigating the malware attack.

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