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公开(公告)号:US20200341766A1
公开(公告)日:2020-10-29
申请号:US16397217
申请日:2019-04-29
Applicant: Intel Corporation
Inventor: Bryan R. White , Ankur N. Shah , Altug Koker , David Puffer , Aditya Navale
IPC: G06F9/30 , G06F12/0831 , G06F12/0837 , G06F9/48 , G06F9/54 , G06F9/38
Abstract: An apparatus to facilitate doorbell notifications is disclosed. The apparatus includes memory-mapped I/O (MMIO) base address registers including a physical function (PF) and plurality of virtual functions (VF), wherein each function's base address register comprises a plurality of doorbell pages and doorbell hardware including doorbell registers, each having an assignable function identifier (ID) and offset, and comprising a plurality of doorbells to activate a doorbell notification in response to receiving a doorbell trigger from an associated doorbell page set upon detection of an access request.
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公开(公告)号:US20190050279A1
公开(公告)日:2019-02-14
申请号:US15818429
申请日:2017-11-20
Applicant: Intel Corporation
Inventor: Michael N. Derr , Balaji Vembu , Michael Mishaeli , Brent Chartrand , Bryan R. White , Gustavo Espinosa , Prashant D. Chaudhari
IPC: G06F11/07
Abstract: Various systems and methods for error handling are described herein. A system for error reporting and handling includes a common error handler that handles errors for a plurality of hardware devices, where the common error handler is operable with other parallel error reporting and handling mechanisms. The common error handler may be used to receive an error message from a hardware device, the error message related to an error; identify a source of the error message; identify a class of the error; identify an error definition of the error; determine whether the error requires a diagnostics operation as part of the error handling; initiate the diagnostics operation when the error requires the diagnostics operation; and clear the error at the hardware device.
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公开(公告)号:US09886934B2
公开(公告)日:2018-02-06
申请号:US14582972
申请日:2014-12-24
Applicant: Intel Corporation
Inventor: Bryan R. White , Balaji Vembu , Murali Ramadoss , Altug Koker , Aditya Navale
CPC classification number: G09G5/18 , G06T1/20 , G09G5/026 , G09G5/14 , G09G5/363 , G09G2320/106 , G09G2340/02 , G09G2360/121 , G09G2360/18 , G09G2370/16
Abstract: Described herein are technologies related to a ensuring that graphics commands and graphics context are offloading and scheduled for consumption as the commands and graphics context are sent from coherent to non-coherent memory/fabric in a “processor to processor” handoff or transaction.
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公开(公告)号:US11341600B2
公开(公告)日:2022-05-24
申请号:US16681983
申请日:2019-11-13
Applicant: Intel Corporation
Inventor: Abhishek R. Appu , Balaji Vembu , Altug Koker , Bryan R. White , David J. Cowperthwaite , Joydeep Ray , Murali Ramadoss
Abstract: An apparatus to facilitate partitioning of a graphics device is disclosed. The apparatus includes a plurality of engines and logic to partition the plurality of engines to facilitate independent access to each engine within the plurality of engines.
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5.
公开(公告)号:US11157431B2
公开(公告)日:2021-10-26
申请号:US16447025
申请日:2019-06-20
Applicant: Intel Corporation
Inventor: Bryan R. White , Aravindh Anantaraman , Ankur Shah , Altug Koker , David Puffer , Aditya Navale
Abstract: In one embodiment, a method includes: receiving, in a root tile of an accelerator device having a plurality of tiles, a message from a processor, the message comprising a register write request to a register of a first remote tile of the plurality of remote tiles; decoding, in an endpoint controller of the root tile, a system address of the message to identify a destination tile for the message, based at least in part on a base address register decode of the system address; and in response to identifying the first remote tile as the destination tile, updating a first portion of an address offset field of the system address to a predetermined value and directing the message to the first remote tile coupled to the root tile via a sideband interconnect. Other embodiments are described and claimed.
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公开(公告)号:US10482562B2
公开(公告)日:2019-11-19
申请号:US15493522
申请日:2017-04-21
Applicant: Intel Corporation
Inventor: Abhishek R. Appu , Balaji Vembu , Altug Koker , Bryan R. White , David J. Cowperthwaite , Joydeep Ray , Murali Ramadoss
Abstract: An apparatus to facilitate partitioning of a graphics device is disclosed. The apparatus includes a plurality of engines and logic to partition the plurality of engines to facilitate independent access to each engine within the plurality of engines.
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公开(公告)号:US20220405876A1
公开(公告)日:2022-12-22
申请号:US17738254
申请日:2022-05-06
Applicant: Intel Corporation
Inventor: Abhishek R. Appu , Balaji Vembu , Altug Koker , Bryan R. White , David J. Cowperthwaite , Joydeep Ray , Murali Ramadoss
Abstract: An apparatus to facilitate partitioning of a graphics device is disclosed. The apparatus includes a plurality of engines and logic to partition the plurality of engines to facilitate independent access to each engine within the plurality of engines.
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公开(公告)号:US10831483B1
公开(公告)日:2020-11-10
申请号:US16397217
申请日:2019-04-29
Applicant: Intel Corporation
Inventor: Bryan R. White , Ankur N. Shah , Altug Koker , David Puffer , Aditya Navale
IPC: G06F9/30 , G06F12/0831 , G06F9/38 , G06F9/48 , G06F9/54 , G06F12/0837
Abstract: An apparatus to facilitate doorbell notifications is disclosed. The apparatus includes memory-mapped I/O (MMIO) base address registers including a physical function (PF) and plurality of virtual functions (VF), wherein each function's base address register comprises a plurality of doorbell pages and doorbell hardware including doorbell registers, each having an assignable function identifier (ID) and offset, and comprising a plurality of doorbells to activate a doorbell notification in response to receiving a doorbell trigger from an associated doorbell page set upon detection of an access request.
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公开(公告)号:US11514550B2
公开(公告)日:2022-11-29
申请号:US16916670
申请日:2020-06-30
Applicant: INTEL CORPORATION
Inventor: Yunbiao Lin , Changliang Wang , Satyanantha Ramagopal Musunuri , David Puffer , David J. Cowperthwaite , Bryan R. White , Balaji Vembu
Abstract: An apparatus and method for managing pipes and planes within a virtual graphics processing engine. For example, one embodiment of a graphics processing apparatus comprises: a graphics processor comprising one or more display pipes to render one or more display planes, each of the one or more display pipes comprising a set of graphics processing hardware resources for executing graphics commands and rendering graphics images in the one or more display planes; and pipe and plane management hardware logic to manage pipe and plane assignment, the pipe and plane management hardware logic to associate a first virtual machine (VM) with one or more virtual display planes and to maintain a mapping between the one or more virtual display planes and at least one physical display plane.
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公开(公告)号:US20220004635A1
公开(公告)日:2022-01-06
申请号:US17480601
申请日:2021-09-21
Applicant: Intel Corporation
Inventor: Daniel Nemiroff , Vidhya Krishnan , Bryan R. White
Abstract: An apparatus is disclosed. The apparatus comprises a trusted device including a first integrated circuit (IC) die comprising a first plurality of hardware devices and a second IC die comprising a second plurality of hardware devices and cryptographic processor to operate as a root of trust to manage an input/output (I/O) functional state of each of the hardware devices.
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