公开(公告)号：US20240126354A1

公开(公告)日：2024-04-18

申请号：US18399224

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Kunal Shah ,  Prabhakar Subrahmanyam ,  Venkataramani Gopalakrishnan ,  Chuen Ming Tan ,  Venkataramana Kotakonda ,  Mitsu Shah ,  Kannappan Rajaraman ,  Yi Jen Huang ,  Dmitriy Berchanskiy ,  Swathi Nukala

IPC: G06F1/26 ,  G06F1/3203

CPC classification number: G06F1/266 ,  G06F1/3203

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed for power budgeting for computer peripherals with electronic devices. An example apparatus to budget power in an electronic device includes interface circuitry; machine readable instructions; and programmable circuitry to at least one of instantiate or execute the machine readable instructions to: detect a Type-C event associated with a computer peripheral; write a power level offset based on an assumed power contract for the computer peripheral during debounce time; obtain an actual power contract for the computer peripheral; and adjust the power level offset based on the actual power contract.

公开(公告)号：US20210109578A1

公开(公告)日：2021-04-15

申请号：US17068709

申请日：2020-10-12

Applicant: Intel Corporation

Inventor： Ashwin Umapathy ,  Chee Lim Nge ,  Timothy Smith ,  Dmitriy Berchanskiy ,  Vinay Raghav

IPC: G06F1/26

Abstract: Three components are used to adjust the CPU peak power based on the USB TYPE-C device states. These components include operating system (OS) Peak Power Manager, USB TYPE-C Connector Manager, and USB TYPE-C Protocol Device Driver. The USB TYPE-C Connector Manager sends a synchronous request to the OS Peak Power Manager when a USB TYPE-C power sink device is attached or detached, and the USB TYPE-C Protocol Device Driver sends a synchronous request to the Peak Power Manager when the power sink transitions device state. The Peak Power Manager takes power budget from the CPU when the USB TYPE-C connector is attached to a power sink and is active (e.g., high power device state), and gives back the power budget to the CPU for performance when the USB TYPE-C connector is either detached or the attached and power sink device is idle (lowest device state).

公开(公告)号：US12242412B2

公开(公告)日：2025-03-04

申请号：US18194262

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Rajaram Regupathy ,  Reuven Rozic ,  Dmitriy Berchanskiy ,  Nirmala Bailur ,  Vrukesh V. Panse ,  Saranya Gopal

IPC: G06F13/42 ,  G06F13/38

Abstract: A data scaling module for USB4 that embodies display driver (DD) and connection manager (CM) operations. Periodic and aperiodic transfer requests are monitored. The periodic BW activity on periodic peripherals, such as display panels (DPs) is monitored, and determinations as to reduced periodic activity on a DP are made. Responsive to receiving a high aperiodic bandwidth request, the original refresh rate for the DP is reduced. The newly freed USB4 BW is provided for the aperiodic task. At completion of the aperiodic task, the DD increases the refresh rate to its original value.

公开(公告)号：US20240330230A1

公开(公告)日：2024-10-03

申请号：US18194262

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Rajaram Regupathy ,  Reuven Rozic ,  Dmitriy Berchanskiy ,  Nirmala Bailur ,  Vrukesh V. Panse ,  Saranya Gopal

IPC: G06F13/42 ,  G06F13/38

CPC classification number: G06F13/4282 ,  G06F13/382 ,  G06F2213/0042

Abstract: A data scaling module for USB4 that embodies display driver (DD) and connection manager (CM) operations. Periodic and aperiodic transfer requests are monitored. The periodic BW activity on periodic peripherals, such as display panels (DPs) is monitored, and determinations as to reduced periodic activity on a DP are made. Responsive to receiving a high aperiodic bandwidth request, the original refresh rate for the DP is reduced. The newly freed USB4 BW is provided for the aperiodic task. At completion of the aperiodic task, the DD increases the refresh rate to its original value.

公开(公告)号：US20250053436A1

公开(公告)日：2025-02-13

申请号：US18723551

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Rajaram Regupathy ,  Reuven Rozic ,  Xiong Zhang ,  Gil Fine ,  Dmitriy Berchanskiy ,  Nirmala Bailur ,  Paul Crutcher

IPC: G06F9/455 ,  G06F13/42

Abstract: In one embodiment, a system comprises: a processor to execute a native operating system (OS); and an interface circuit coupled to the processor, the interface circuit configured to tunnel communications of a plurality of tunneled protocols, the interface circuit to couple to at least one device via a first tunneled protocol, where a connection manager for the interface circuit is to execute in a user space of the native OS. Other embodiments are described and claimed.

公开(公告)号：US11940855B2

公开(公告)日：2024-03-26

申请号：US17068709

申请日：2020-10-12

Applicant: Intel Corporation

Inventor： Ashwin Umapathy ,  Chee Lim Nge ,  Timothy Smith ,  Dmitriy Berchanskiy ,  Vinay Raghav

IPC: G06F1/26

CPC classification number: G06F1/26

Abstract: Three components are used to adjust the CPU peak power based on the USB TYPE-C device states. These components include operating system (OS) Peak Power Manager, USB TYPE-C Connector Manager, and USB TYPE-C Protocol Device Driver. The USB TYPE-C Connector Manager sends a synchronous request to the OS Peak Power Manager when a USB TYPE-C power sink device is attached or detached, and the USB TYPE-C Protocol Device Driver sends a synchronous request to the Peak Power Manager when the power sink transitions device state. The Peak Power Manager takes power budget from the CPU when the USB TYPE-C connector is attached to a power sink and is active (e.g., high power device state), and gives back the power budget to the CPU for performance when the USB TYPE-C connector is either detached or the attached and power sink device is idle (lowest device state).

公开(公告)号：US20230350479A1

公开(公告)日：2023-11-02

申请号：US17732096

申请日：2022-04-28

Applicant: Intel Corporation

Inventor： Venkataramani Gopalakrishnan ,  Chuen Ming Tan ,  Divagar Mohandass ,  Dmitriy Berchanskiy ,  Nirmala Bailur ,  Timothy Smith ,  Rajaram Regupathy

IPC: G06F1/3215 ,  G06F1/3212 ,  G06F1/3296

CPC classification number: G06F1/3215 ,  G06F1/3212 ,  G06F1/3296

Abstract: Systems, apparatuses and methods may provide for technology that allocates a portion of operational power in a source device to an external sink device in response to a connection of the external sink device to the source device, detects a low power state with respect to the external sink device, and decreases the portion of operational power allocated to the external sink device in response to the low power state.

公开(公告)号：US11347673B2

公开(公告)日：2022-05-31

申请号：US15721831

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Dmitriy Berchanskiy ,  Venkataramani Gopalakrishnan ,  Jose A. Meza Arellano ,  James E. Akiyama ,  Kevin Southern

IPC: G06F13/40 ,  G06F13/38 ,  G06F3/14 ,  G06F13/42 ,  G06T1/20

Abstract: Aspects of the embodiments are directed to a ThunderBolt (TBT) input/output (I/O) controller apparatus. The TBT I/O controller apparatus can include an output port to receive a connection to a display device; a multiplexer coupled to the output port; a first input port coupled to the multiplexer; a second input port coupled to the multiplexer; a memory element to store graphics preference data; and TBT firmware (FW). The TBT FW can detect a connected device at the input port; determine a graphics processor for the connected device based on the graphics preference data; and logically connect the connected device to one of the first input port or the second input port through the multiplexer based on the determined graphics processor.

公开(公告)号：US11157068B2

公开(公告)日：2021-10-26

申请号：US16258355

申请日：2019-01-25

Applicant: Intel Corporation

Inventor： Dmitriy Berchanskiy ,  Vinay Raghav ,  Udaya Natarajan ,  Huimin Chen

IPC: G06F1/3234 ,  G06F1/329 ,  G06F1/26 ,  G06F1/3228 ,  G06F1/3287

Abstract: Embodiments may include systems and methods for communication including a communication port with a first lane and a second lane, a first power controller and a second power controller coupled to the communication port. The first power controller is to control, at a first time instance, the first lane to operate in a first power state selected from a first set of power states for the first lane. The second power controller is to control, at a second time instance, the second lane to operate in a second power state selected from a second set of power states for the second lane, wherein the first power state is different from the second power state. Other embodiments may be described and/or claimed.

公开(公告)号：US20190102334A1

公开(公告)日：2019-04-04

申请号：US15721831

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Dmitriy Berchanskiy ,  Venkataramani Gopalakrishnan ,  Jose A. Meza Arellano ,  James E. Akiyama ,  Kevin Southern

IPC: G06F13/40 ,  G06F13/42 ,  G06T1/20

Abstract: Aspects of the embodiments are directed to a ThunderBolt (TBT) input/output (I/O) controller apparatus. The TBT I/O controller apparatus can include an output port to receive a connection to a display device; a multiplexer coupled to the output port; a first input port coupled to the multiplexer; a second input port coupled to the multiplexer; a memory element to store graphics preference data; and TBT firmware (FW). The TBT FW can detect a connected device at the input port; determine a graphics processor for the connected device based on the graphics preference data; and logically connect the connected device to one of the first input port or the second input port through the multiplexer based on the determined graphics processor.